powerpc/eeh: Replace device_node with pci_dn in eeh_ops
There are 3 EEH operations whose arguments contain device_node: read_config(), write_config() and restore_config(). The patch replaces device_node with pci_dn. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Gavin Shan
Benjamin Herrenschmidt
parent
ff57b454dd
commit
0bd785873c
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@ -217,10 +217,10 @@ struct eeh_ops {
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int (*configure_bridge)(struct eeh_pe *pe);
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int (*err_inject)(struct eeh_pe *pe, int type, int func,
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unsigned long addr, unsigned long mask);
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int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
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int (*write_config)(struct device_node *dn, int where, int size, u32 val);
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int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val);
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int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val);
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int (*next_error)(struct eeh_pe **pe);
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int (*restore_config)(struct device_node *dn);
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int (*restore_config)(struct pci_dn *pdn);
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};
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extern int eeh_subsystem_flags;
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@ -164,30 +164,34 @@ __setup("eeh=", eeh_setup);
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*/
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static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
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{
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struct device_node *dn = eeh_dev_to_of_node(edev);
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struct pci_dn *pdn = eeh_dev_to_pdn(edev);
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u32 cfg;
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int cap, i;
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int n = 0, l = 0;
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char buffer[128];
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n += scnprintf(buf+n, len-n, "%s\n", dn->full_name);
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pr_warn("EEH: of node=%s\n", dn->full_name);
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n += scnprintf(buf+n, len-n, "%04x:%02x:%02x:%01x\n",
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edev->phb->global_number, pdn->busno,
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PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
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pr_warn("EEH: of node=%04x:%02x:%02x:%01x\n",
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edev->phb->global_number, pdn->busno,
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PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
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eeh_ops->read_config(dn, PCI_VENDOR_ID, 4, &cfg);
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eeh_ops->read_config(pdn, PCI_VENDOR_ID, 4, &cfg);
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n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
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pr_warn("EEH: PCI device/vendor: %08x\n", cfg);
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eeh_ops->read_config(dn, PCI_COMMAND, 4, &cfg);
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eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cfg);
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n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
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pr_warn("EEH: PCI cmd/status register: %08x\n", cfg);
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/* Gather bridge-specific registers */
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if (edev->mode & EEH_DEV_BRIDGE) {
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eeh_ops->read_config(dn, PCI_SEC_STATUS, 2, &cfg);
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eeh_ops->read_config(pdn, PCI_SEC_STATUS, 2, &cfg);
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n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
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pr_warn("EEH: Bridge secondary status: %04x\n", cfg);
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eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &cfg);
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eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg);
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n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
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pr_warn("EEH: Bridge control: %04x\n", cfg);
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}
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@ -195,11 +199,11 @@ static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
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/* Dump out the PCI-X command and status regs */
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cap = edev->pcix_cap;
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if (cap) {
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eeh_ops->read_config(dn, cap, 4, &cfg);
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eeh_ops->read_config(pdn, cap, 4, &cfg);
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n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
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pr_warn("EEH: PCI-X cmd: %08x\n", cfg);
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eeh_ops->read_config(dn, cap+4, 4, &cfg);
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eeh_ops->read_config(pdn, cap+4, 4, &cfg);
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n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
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pr_warn("EEH: PCI-X status: %08x\n", cfg);
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}
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@ -211,7 +215,7 @@ static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
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pr_warn("EEH: PCI-E capabilities and status follow:\n");
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for (i=0; i<=8; i++) {
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eeh_ops->read_config(dn, cap+4*i, 4, &cfg);
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eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
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n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
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if ((i % 4) == 0) {
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@ -238,7 +242,7 @@ static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
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pr_warn("EEH: PCI-E AER capability register set follows:\n");
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for (i=0; i<=13; i++) {
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eeh_ops->read_config(dn, cap+4*i, 4, &cfg);
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eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
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n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
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if ((i % 4) == 0) {
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@ -698,7 +702,7 @@ static void *eeh_disable_and_save_dev_state(void *data, void *userdata)
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static void *eeh_restore_dev_state(void *data, void *userdata)
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{
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struct eeh_dev *edev = data;
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struct device_node *dn = eeh_dev_to_of_node(edev);
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struct pci_dn *pdn = eeh_dev_to_pdn(edev);
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struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
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struct pci_dev *dev = userdata;
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@ -706,8 +710,8 @@ static void *eeh_restore_dev_state(void *data, void *userdata)
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return NULL;
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/* Apply customization from firmware */
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if (dn && eeh_ops->restore_config)
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eeh_ops->restore_config(dn);
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if (pdn && eeh_ops->restore_config)
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eeh_ops->restore_config(pdn);
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/* The caller should restore state for the specified device */
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if (pdev != dev)
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@ -870,15 +874,15 @@ out:
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*/
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void eeh_save_bars(struct eeh_dev *edev)
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{
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struct pci_dn *pdn;
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int i;
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struct device_node *dn;
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if (!edev)
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pdn = eeh_dev_to_pdn(edev);
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if (!pdn)
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return;
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dn = eeh_dev_to_of_node(edev);
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for (i = 0; i < 16; i++)
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eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]);
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eeh_ops->read_config(pdn, i * 4, 4, &edev->config_space[i]);
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/*
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* For PCI bridges including root port, we need enable bus
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@ -291,27 +291,25 @@ struct eeh_pe *eeh_pe_get(struct eeh_dev *edev)
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*/
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static struct eeh_pe *eeh_pe_get_parent(struct eeh_dev *edev)
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{
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struct device_node *dn;
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struct eeh_dev *parent;
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struct pci_dn *pdn = eeh_dev_to_pdn(edev);
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/*
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* It might have the case for the indirect parent
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* EEH device already having associated PE, but
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* the direct parent EEH device doesn't have yet.
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*/
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dn = edev->dn->parent;
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while (dn) {
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pdn = pdn ? pdn->parent : NULL;
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while (pdn) {
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/* We're poking out of PCI territory */
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if (!PCI_DN(dn)) return NULL;
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parent = of_node_to_eeh_dev(dn);
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/* We're poking out of PCI territory */
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if (!parent) return NULL;
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parent = pdn_to_eeh_dev(pdn);
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if (!parent)
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return NULL;
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if (parent->pe)
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return parent->pe;
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dn = dn->parent;
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pdn = pdn->parent;
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}
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return NULL;
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@ -653,9 +651,9 @@ void eeh_pe_state_clear(struct eeh_pe *pe, int state)
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* blocked on normal path during the stage. So we need utilize
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* eeh operations, which is always permitted.
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*/
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static void eeh_bridge_check_link(struct eeh_dev *edev,
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struct device_node *dn)
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static void eeh_bridge_check_link(struct eeh_dev *edev)
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{
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struct pci_dn *pdn = eeh_dev_to_pdn(edev);
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int cap;
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uint32_t val;
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int timeout = 0;
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@ -675,32 +673,32 @@ static void eeh_bridge_check_link(struct eeh_dev *edev,
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/* Check slot status */
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cap = edev->pcie_cap;
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eeh_ops->read_config(dn, cap + PCI_EXP_SLTSTA, 2, &val);
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eeh_ops->read_config(pdn, cap + PCI_EXP_SLTSTA, 2, &val);
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if (!(val & PCI_EXP_SLTSTA_PDS)) {
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pr_debug(" No card in the slot (0x%04x) !\n", val);
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return;
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}
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/* Check power status if we have the capability */
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eeh_ops->read_config(dn, cap + PCI_EXP_SLTCAP, 2, &val);
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eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCAP, 2, &val);
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if (val & PCI_EXP_SLTCAP_PCP) {
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eeh_ops->read_config(dn, cap + PCI_EXP_SLTCTL, 2, &val);
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eeh_ops->read_config(pdn, cap + PCI_EXP_SLTCTL, 2, &val);
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if (val & PCI_EXP_SLTCTL_PCC) {
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pr_debug(" In power-off state, power it on ...\n");
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val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
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val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
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eeh_ops->write_config(dn, cap + PCI_EXP_SLTCTL, 2, val);
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eeh_ops->write_config(pdn, cap + PCI_EXP_SLTCTL, 2, val);
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msleep(2 * 1000);
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}
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}
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/* Enable link */
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eeh_ops->read_config(dn, cap + PCI_EXP_LNKCTL, 2, &val);
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eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCTL, 2, &val);
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val &= ~PCI_EXP_LNKCTL_LD;
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eeh_ops->write_config(dn, cap + PCI_EXP_LNKCTL, 2, val);
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eeh_ops->write_config(pdn, cap + PCI_EXP_LNKCTL, 2, val);
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/* Check link */
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eeh_ops->read_config(dn, cap + PCI_EXP_LNKCAP, 4, &val);
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eeh_ops->read_config(pdn, cap + PCI_EXP_LNKCAP, 4, &val);
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if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
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pr_debug(" No link reporting capability (0x%08x) \n", val);
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msleep(1000);
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@ -713,7 +711,7 @@ static void eeh_bridge_check_link(struct eeh_dev *edev,
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msleep(20);
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timeout += 20;
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eeh_ops->read_config(dn, cap + PCI_EXP_LNKSTA, 2, &val);
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eeh_ops->read_config(pdn, cap + PCI_EXP_LNKSTA, 2, &val);
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if (val & PCI_EXP_LNKSTA_DLLLA)
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break;
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}
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@ -728,9 +726,9 @@ static void eeh_bridge_check_link(struct eeh_dev *edev,
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#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
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#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
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static void eeh_restore_bridge_bars(struct eeh_dev *edev,
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struct device_node *dn)
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static void eeh_restore_bridge_bars(struct eeh_dev *edev)
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{
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struct pci_dn *pdn = eeh_dev_to_pdn(edev);
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int i;
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/*
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@ -738,49 +736,49 @@ static void eeh_restore_bridge_bars(struct eeh_dev *edev,
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* Bus numbers and windows: 0x18 - 0x30
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*/
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for (i = 4; i < 13; i++)
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eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
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eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
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/* Rom: 0x38 */
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eeh_ops->write_config(dn, 14*4, 4, edev->config_space[14]);
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eeh_ops->write_config(pdn, 14*4, 4, edev->config_space[14]);
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/* Cache line & Latency timer: 0xC 0xD */
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eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
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eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
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SAVED_BYTE(PCI_CACHE_LINE_SIZE));
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eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
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eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
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SAVED_BYTE(PCI_LATENCY_TIMER));
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/* Max latency, min grant, interrupt ping and line: 0x3C */
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eeh_ops->write_config(dn, 15*4, 4, edev->config_space[15]);
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eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
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/* PCI Command: 0x4 */
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eeh_ops->write_config(dn, PCI_COMMAND, 4, edev->config_space[1]);
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eeh_ops->write_config(pdn, PCI_COMMAND, 4, edev->config_space[1]);
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/* Check the PCIe link is ready */
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eeh_bridge_check_link(edev, dn);
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eeh_bridge_check_link(edev);
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}
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static void eeh_restore_device_bars(struct eeh_dev *edev,
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struct device_node *dn)
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static void eeh_restore_device_bars(struct eeh_dev *edev)
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{
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struct pci_dn *pdn = eeh_dev_to_pdn(edev);
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int i;
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u32 cmd;
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for (i = 4; i < 10; i++)
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eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
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eeh_ops->write_config(pdn, i*4, 4, edev->config_space[i]);
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/* 12 == Expansion ROM Address */
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eeh_ops->write_config(dn, 12*4, 4, edev->config_space[12]);
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eeh_ops->write_config(pdn, 12*4, 4, edev->config_space[12]);
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eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
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eeh_ops->write_config(pdn, PCI_CACHE_LINE_SIZE, 1,
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SAVED_BYTE(PCI_CACHE_LINE_SIZE));
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eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
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eeh_ops->write_config(pdn, PCI_LATENCY_TIMER, 1,
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SAVED_BYTE(PCI_LATENCY_TIMER));
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/* max latency, min grant, interrupt pin and line */
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eeh_ops->write_config(dn, 15*4, 4, edev->config_space[15]);
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eeh_ops->write_config(pdn, 15*4, 4, edev->config_space[15]);
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/*
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* Restore PERR & SERR bits, some devices require it,
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* don't touch the other command bits
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*/
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eeh_ops->read_config(dn, PCI_COMMAND, 4, &cmd);
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eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cmd);
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if (edev->config_space[1] & PCI_COMMAND_PARITY)
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cmd |= PCI_COMMAND_PARITY;
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else
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@ -789,7 +787,7 @@ static void eeh_restore_device_bars(struct eeh_dev *edev,
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cmd |= PCI_COMMAND_SERR;
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else
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cmd &= ~PCI_COMMAND_SERR;
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eeh_ops->write_config(dn, PCI_COMMAND, 4, cmd);
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eeh_ops->write_config(pdn, PCI_COMMAND, 4, cmd);
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}
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/**
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@ -804,16 +802,16 @@ static void eeh_restore_device_bars(struct eeh_dev *edev,
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static void *eeh_restore_one_device_bars(void *data, void *flag)
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{
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struct eeh_dev *edev = (struct eeh_dev *)data;
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struct device_node *dn = eeh_dev_to_of_node(edev);
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struct pci_dn *pdn = eeh_dev_to_pdn(edev);
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/* Do special restore for bridges */
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if (edev->mode & EEH_DEV_BRIDGE)
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eeh_restore_bridge_bars(edev, dn);
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eeh_restore_bridge_bars(edev);
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else
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eeh_restore_device_bars(edev, dn);
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eeh_restore_device_bars(edev);
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if (eeh_ops->restore_config)
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eeh_ops->restore_config(dn);
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if (eeh_ops->restore_config && pdn)
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eeh_ops->restore_config(pdn);
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return NULL;
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}
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@ -842,8 +842,8 @@ out:
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static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option)
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{
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struct device_node *dn = pci_device_to_OF_node(dev);
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struct eeh_dev *edev = of_node_to_eeh_dev(dn);
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struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
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struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
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int aer = edev ? edev->aer_cap : 0;
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u32 ctrl;
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@ -856,32 +856,32 @@ static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option)
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case EEH_RESET_HOT:
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/* Don't report linkDown event */
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if (aer) {
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eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK,
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eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
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4, &ctrl);
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ctrl |= PCI_ERR_UNC_SURPDN;
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eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK,
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eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
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4, ctrl);
|
||||
}
|
||||
|
||||
eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &ctrl);
|
||||
eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
|
||||
ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
|
||||
eeh_ops->write_config(dn, PCI_BRIDGE_CONTROL, 2, ctrl);
|
||||
eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
|
||||
|
||||
msleep(EEH_PE_RST_HOLD_TIME);
|
||||
break;
|
||||
case EEH_RESET_DEACTIVATE:
|
||||
eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &ctrl);
|
||||
eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
|
||||
ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
|
||||
eeh_ops->write_config(dn, PCI_BRIDGE_CONTROL, 2, ctrl);
|
||||
eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
|
||||
|
||||
msleep(EEH_PE_RST_SETTLE_TIME);
|
||||
|
||||
/* Continue reporting linkDown event */
|
||||
if (aer) {
|
||||
eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK,
|
||||
eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
|
||||
4, &ctrl);
|
||||
ctrl &= ~PCI_ERR_UNC_SURPDN;
|
||||
eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK,
|
||||
eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
|
||||
4, ctrl);
|
||||
}
|
||||
|
||||
|
|
@ -1099,9 +1099,9 @@ static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline bool pnv_eeh_cfg_blocked(struct device_node *dn)
|
||||
static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn)
|
||||
{
|
||||
struct eeh_dev *edev = of_node_to_eeh_dev(dn);
|
||||
struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
|
||||
|
||||
if (!edev || !edev->pe)
|
||||
return false;
|
||||
|
|
@ -1112,15 +1112,13 @@ static inline bool pnv_eeh_cfg_blocked(struct device_node *dn)
|
|||
return false;
|
||||
}
|
||||
|
||||
static int pnv_eeh_read_config(struct device_node *dn,
|
||||
static int pnv_eeh_read_config(struct pci_dn *pdn,
|
||||
int where, int size, u32 *val)
|
||||
{
|
||||
struct pci_dn *pdn = PCI_DN(dn);
|
||||
|
||||
if (!pdn)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
if (pnv_eeh_cfg_blocked(dn)) {
|
||||
if (pnv_eeh_cfg_blocked(pdn)) {
|
||||
*val = 0xFFFFFFFF;
|
||||
return PCIBIOS_SET_FAILED;
|
||||
}
|
||||
|
|
@ -1128,15 +1126,13 @@ static int pnv_eeh_read_config(struct device_node *dn,
|
|||
return pnv_pci_cfg_read(pdn, where, size, val);
|
||||
}
|
||||
|
||||
static int pnv_eeh_write_config(struct device_node *dn,
|
||||
static int pnv_eeh_write_config(struct pci_dn *pdn,
|
||||
int where, int size, u32 val)
|
||||
{
|
||||
struct pci_dn *pdn = PCI_DN(dn);
|
||||
|
||||
if (!pdn)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
if (pnv_eeh_cfg_blocked(dn))
|
||||
if (pnv_eeh_cfg_blocked(pdn))
|
||||
return PCIBIOS_SET_FAILED;
|
||||
|
||||
return pnv_pci_cfg_write(pdn, where, size, val);
|
||||
|
|
@ -1484,9 +1480,9 @@ static int pnv_eeh_next_error(struct eeh_pe **pe)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int pnv_eeh_restore_config(struct device_node *dn)
|
||||
static int pnv_eeh_restore_config(struct pci_dn *pdn)
|
||||
{
|
||||
struct eeh_dev *edev = of_node_to_eeh_dev(dn);
|
||||
struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
|
||||
struct pnv_phb *phb;
|
||||
s64 ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -651,37 +651,29 @@ static int pseries_eeh_configure_bridge(struct eeh_pe *pe)
|
|||
|
||||
/**
|
||||
* pseries_eeh_read_config - Read PCI config space
|
||||
* @dn: device node
|
||||
* @pdn: PCI device node
|
||||
* @where: PCI address
|
||||
* @size: size to read
|
||||
* @val: return value
|
||||
*
|
||||
* Read config space from the speicifed device
|
||||
*/
|
||||
static int pseries_eeh_read_config(struct device_node *dn, int where, int size, u32 *val)
|
||||
static int pseries_eeh_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
|
||||
{
|
||||
struct pci_dn *pdn;
|
||||
|
||||
pdn = PCI_DN(dn);
|
||||
|
||||
return rtas_read_config(pdn, where, size, val);
|
||||
}
|
||||
|
||||
/**
|
||||
* pseries_eeh_write_config - Write PCI config space
|
||||
* @dn: device node
|
||||
* @pdn: PCI device node
|
||||
* @where: PCI address
|
||||
* @size: size to write
|
||||
* @val: value to be written
|
||||
*
|
||||
* Write config space to the specified device
|
||||
*/
|
||||
static int pseries_eeh_write_config(struct device_node *dn, int where, int size, u32 val)
|
||||
static int pseries_eeh_write_config(struct pci_dn *pdn, int where, int size, u32 val)
|
||||
{
|
||||
struct pci_dn *pdn;
|
||||
|
||||
pdn = PCI_DN(dn);
|
||||
|
||||
return rtas_write_config(pdn, where, size, val);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue