mtd: nand: remove a bunch of unused commands
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Artem Bityutskiy
David Woodhouse
parent
14c6578683
commit
0be718e552
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@ -303,13 +303,7 @@ static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
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case NAND_CMD_SEQIN:
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case NAND_CMD_RNDIN:
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case NAND_CMD_STATUS:
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case NAND_CMD_DEPLETE1:
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case NAND_CMD_RNDOUT:
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case NAND_CMD_STATUS_ERROR:
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case NAND_CMD_STATUS_ERROR0:
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case NAND_CMD_STATUS_ERROR1:
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case NAND_CMD_STATUS_ERROR2:
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case NAND_CMD_STATUS_ERROR3:
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cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
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return;
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}
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@ -668,16 +668,6 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
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case NAND_CMD_SEQIN:
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case NAND_CMD_RNDIN:
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case NAND_CMD_STATUS:
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case NAND_CMD_DEPLETE1:
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return;
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case NAND_CMD_STATUS_ERROR:
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case NAND_CMD_STATUS_ERROR0:
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case NAND_CMD_STATUS_ERROR1:
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case NAND_CMD_STATUS_ERROR2:
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case NAND_CMD_STATUS_ERROR3:
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/* Read error status commands require only a short delay */
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udelay(chip->chip_delay);
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return;
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case NAND_CMD_RESET:
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@ -218,7 +218,6 @@ MODULE_PARM_DESC(bch, "Enable BCH ecc and set how many bits should "
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#define STATE_CMD_READOOB 0x00000005 /* read OOB area */
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#define STATE_CMD_ERASE1 0x00000006 /* sector erase first command */
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#define STATE_CMD_STATUS 0x00000007 /* read status */
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#define STATE_CMD_STATUS_M 0x00000008 /* read multi-plane status (isn't implemented) */
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#define STATE_CMD_SEQIN 0x00000009 /* sequential data input */
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#define STATE_CMD_READID 0x0000000A /* read ID */
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#define STATE_CMD_ERASE2 0x0000000B /* sector erase second command */
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@ -406,8 +405,6 @@ static struct nandsim_operations {
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{OPT_ANY, {STATE_CMD_ERASE1, STATE_ADDR_SEC, STATE_CMD_ERASE2 | ACTION_SECERASE, STATE_READY}},
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/* Read status */
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{OPT_ANY, {STATE_CMD_STATUS, STATE_DATAOUT_STATUS, STATE_READY}},
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/* Read multi-plane status */
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{OPT_SMARTMEDIA, {STATE_CMD_STATUS_M, STATE_DATAOUT_STATUS_M, STATE_READY}},
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/* Read ID */
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{OPT_ANY, {STATE_CMD_READID, STATE_ADDR_ZERO, STATE_DATAOUT_ID, STATE_READY}},
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/* Large page devices read page */
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@ -1079,8 +1076,6 @@ static char *get_state_name(uint32_t state)
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return "STATE_CMD_ERASE1";
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case STATE_CMD_STATUS:
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return "STATE_CMD_STATUS";
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case STATE_CMD_STATUS_M:
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return "STATE_CMD_STATUS_M";
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case STATE_CMD_SEQIN:
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return "STATE_CMD_SEQIN";
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case STATE_CMD_READID:
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@ -1145,7 +1140,6 @@ static int check_command(int cmd)
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case NAND_CMD_RNDOUTSTART:
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return 0;
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case NAND_CMD_STATUS_MULTI:
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default:
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return 1;
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}
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@ -1171,8 +1165,6 @@ static uint32_t get_state_by_command(unsigned command)
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return STATE_CMD_ERASE1;
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case NAND_CMD_STATUS:
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return STATE_CMD_STATUS;
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case NAND_CMD_STATUS_MULTI:
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return STATE_CMD_STATUS_M;
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case NAND_CMD_SEQIN:
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return STATE_CMD_SEQIN;
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case NAND_CMD_READID:
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@ -177,15 +177,6 @@ static void nuc900_nand_command_lp(struct mtd_info *mtd, unsigned int command,
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case NAND_CMD_SEQIN:
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case NAND_CMD_RNDIN:
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case NAND_CMD_STATUS:
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case NAND_CMD_DEPLETE1:
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return;
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case NAND_CMD_STATUS_ERROR:
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case NAND_CMD_STATUS_ERROR0:
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case NAND_CMD_STATUS_ERROR1:
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case NAND_CMD_STATUS_ERROR2:
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case NAND_CMD_STATUS_ERROR3:
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udelay(chip->chip_delay);
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return;
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case NAND_CMD_RESET:
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@ -86,7 +86,6 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
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#define NAND_CMD_READOOB 0x50
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#define NAND_CMD_ERASE1 0x60
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#define NAND_CMD_STATUS 0x70
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#define NAND_CMD_STATUS_MULTI 0x71
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#define NAND_CMD_SEQIN 0x80
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#define NAND_CMD_RNDIN 0x85
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#define NAND_CMD_READID 0x90
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@ -105,25 +104,6 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
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#define NAND_CMD_RNDOUTSTART 0xE0
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#define NAND_CMD_CACHEDPROG 0x15
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/* Extended commands for AG-AND device */
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/*
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* Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
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* there is no way to distinguish that from NAND_CMD_READ0
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* until the remaining sequence of commands has been completed
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* so add a high order bit and mask it off in the command.
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*/
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#define NAND_CMD_DEPLETE1 0x100
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#define NAND_CMD_DEPLETE2 0x38
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#define NAND_CMD_STATUS_MULTI 0x71
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#define NAND_CMD_STATUS_ERROR 0x72
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/* multi-bank error status (banks 0-3) */
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#define NAND_CMD_STATUS_ERROR0 0x73
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#define NAND_CMD_STATUS_ERROR1 0x74
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#define NAND_CMD_STATUS_ERROR2 0x75
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#define NAND_CMD_STATUS_ERROR3 0x76
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#define NAND_CMD_STATUS_RESET 0x7f
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#define NAND_CMD_STATUS_CLEAR 0xff
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#define NAND_CMD_NONE -1
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/* Status bits */
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