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drm/i915/pps: move pps code over from intel_display.c and refactor
intel_display.c has some pps functions that belong to intel_pps.c. Move them over. While at it, refactor the duplicate intel_pps_init() in intel_display.c into an orthogonal intel_pps_setup() in intel_pps.c, and call it earlier in intel_modeset_init_nogem(). Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210120101834.19813-2-jani.nikula@intel.com
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parent
97b70144b2
commit
0bf1e5a852
5 changed files with 42 additions and 38 deletions
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@ -83,6 +83,7 @@
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#include "intel_overlay.h"
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#include "intel_pipe_crc.h"
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#include "intel_pm.h"
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#include "intel_pps.h"
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#include "intel_psr.h"
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#include "intel_quirks.h"
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#include "intel_sideband.h"
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@ -13795,48 +13796,12 @@ static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
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return true;
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}
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void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
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{
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int pps_num;
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int pps_idx;
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if (HAS_DDI(dev_priv))
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return;
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/*
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* This w/a is needed at least on CPT/PPT, but to be sure apply it
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* everywhere where registers can be write protected.
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*/
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if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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pps_num = 2;
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else
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pps_num = 1;
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for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
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u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
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val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
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intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
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}
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}
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static void intel_pps_init(struct drm_i915_private *dev_priv)
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{
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if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
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dev_priv->pps_mmio_base = PCH_PPS_BASE;
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else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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dev_priv->pps_mmio_base = VLV_PPS_BASE;
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else
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dev_priv->pps_mmio_base = PPS_BASE;
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intel_pps_unlock_regs_wa(dev_priv);
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}
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static void intel_setup_outputs(struct drm_i915_private *dev_priv)
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{
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struct intel_encoder *encoder;
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bool dpd_is_edp = false;
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intel_pps_init(dev_priv);
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intel_pps_unlock_regs_wa(dev_priv);
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if (!HAS_DISPLAY(dev_priv))
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return;
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@ -14848,6 +14813,8 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
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intel_panel_sanitize_ssc(i915);
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intel_pps_setup(i915);
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intel_gmbus_setup(i915);
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drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
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@ -546,7 +546,6 @@ unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info
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unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
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bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
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int intel_display_suspend(struct drm_device *dev);
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void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
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void intel_encoder_destroy(struct drm_encoder *encoder);
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struct drm_display_mode *
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intel_encoder_current_mode(struct intel_encoder *encoder);
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@ -1370,3 +1370,37 @@ void intel_pps_init(struct intel_dp *intel_dp)
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intel_pps_encoder_reset(intel_dp);
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}
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void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
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{
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int pps_num;
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int pps_idx;
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if (HAS_DDI(dev_priv))
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return;
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/*
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* This w/a is needed at least on CPT/PPT, but to be sure apply it
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* everywhere where registers can be write protected.
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*/
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if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
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pps_num = 2;
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else
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pps_num = 1;
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for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
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u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx));
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val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
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intel_de_write(dev_priv, PP_CONTROL(pps_idx), val);
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}
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}
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void intel_pps_setup(struct drm_i915_private *i915)
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{
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if (HAS_PCH_SPLIT(i915) || IS_GEN9_LP(i915))
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i915->pps_mmio_base = PCH_PPS_BASE;
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else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
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i915->pps_mmio_base = VLV_PPS_BASE;
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else
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i915->pps_mmio_base = PPS_BASE;
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}
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@ -46,4 +46,7 @@ void intel_pps_reset_all(struct drm_i915_private *i915);
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void vlv_pps_init(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void intel_pps_unlock_regs_wa(struct drm_i915_private *i915);
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void intel_pps_setup(struct drm_i915_private *i915);
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#endif /* __INTEL_PPS_H__ */
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@ -58,6 +58,7 @@
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#include "display/intel_hotplug.h"
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#include "display/intel_overlay.h"
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#include "display/intel_pipe_crc.h"
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#include "display/intel_pps.h"
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#include "display/intel_sprite.h"
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#include "display/intel_vga.h"
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