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drm/amdgpu: switch to use smuio callbacks for NV family
Switch to smuio callbacks: use smuio v11_0_6 callbacks for Sienna_cichlid and forward ASIC, use smuio v11_0 callbacks for the other NV family ASIC. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 15 additions and 3 deletions
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@ -38,7 +38,6 @@
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#include "gc/gc_10_1_0_offset.h"
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#include "gc/gc_10_1_0_sh_mask.h"
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#include "smuio/smuio_11_0_0_offset.h"
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#include "mp/mp_11_0_offset.h"
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#include "soc15.h"
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@ -61,6 +60,8 @@
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#include "dce_virtual.h"
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#include "mes_v10_1.h"
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#include "mxgpu_nv.h"
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#include "smuio_v11_0.h"
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#include "smuio_v11_0_6.h"
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static const struct amd_ip_funcs nv_common_ip_funcs;
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@ -202,6 +203,7 @@ static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
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{
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u32 *dw_ptr;
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u32 i, length_dw;
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u32 rom_index_offset, rom_data_offset;
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if (bios == NULL)
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return false;
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@ -214,11 +216,16 @@ static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
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dw_ptr = (u32 *)bios;
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length_dw = ALIGN(length_bytes, 4) / 4;
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rom_index_offset =
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adev->smuio.funcs->get_rom_index_offset(adev);
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rom_data_offset =
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adev->smuio.funcs->get_rom_data_offset(adev);
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/* set rom index to 0 */
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WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
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WREG32(rom_index_offset, 0);
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/* read out the rom data */
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for (i = 0; i < length_dw; i++)
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dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
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dw_ptr[i] = RREG32(rom_data_offset);
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return true;
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}
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@ -564,6 +571,11 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
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}
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adev->hdp.funcs = &hdp_v5_0_funcs;
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if (adev->asic_type >= CHIP_SIENNA_CICHLID)
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adev->smuio.funcs = &smuio_v11_0_6_funcs;
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else
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adev->smuio.funcs = &smuio_v11_0_funcs;
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if (adev->asic_type == CHIP_SIENNA_CICHLID)
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adev->gmc.xgmi.supported = true;
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