mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-05 18:39:59 +00:00
mt76: mt7921: add wifi reset support
Introduce wifi chip reset support for mt7921 device to recover mcu hangs. Co-developed-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
parent
c001df978e
commit
0c1ce98846
5 changed files with 155 additions and 60 deletions
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@ -143,7 +143,7 @@ mt7921_mac_init_band(struct mt7921_dev *dev, u8 band)
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mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN);
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}
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static void mt7921_mac_init(struct mt7921_dev *dev)
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void mt7921_mac_init(struct mt7921_dev *dev)
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{
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int i;
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@ -233,7 +233,6 @@ int mt7921_register_device(struct mt7921_dev *dev)
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INIT_LIST_HEAD(&dev->sta_poll_list);
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spin_lock_init(&dev->sta_poll_lock);
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init_waitqueue_head(&dev->reset_wait);
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INIT_WORK(&dev->reset_work, mt7921_mac_reset_work);
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ret = mt7921_init_hardware(dev);
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@ -1184,43 +1184,77 @@ void mt7921_update_channel(struct mt76_dev *mdev)
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mt76_connac_power_save_sched(&dev->mphy, &dev->pm);
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}
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static bool
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mt7921_wait_reset_state(struct mt7921_dev *dev, u32 state)
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static int
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mt7921_wfsys_reset(struct mt7921_dev *dev)
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{
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bool ret;
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mt76_set(dev, 0x70002600, BIT(0));
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msleep(200);
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mt76_clear(dev, 0x70002600, BIT(0));
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ret = wait_event_timeout(dev->reset_wait,
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(READ_ONCE(dev->reset_state) & state),
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MT7921_RESET_TIMEOUT);
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WARN(!ret, "Timeout waiting for MCU reset state %x\n", state);
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return ret;
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return __mt76_poll_msec(&dev->mt76, MT_WFSYS_SW_RST_B,
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WFSYS_SW_INIT_DONE, WFSYS_SW_INIT_DONE, 500);
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}
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static void
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mt7921_dma_reset(struct mt7921_phy *phy)
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mt7921_dma_reset(struct mt7921_dev *dev)
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{
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struct mt7921_dev *dev = phy->dev;
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int i;
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/* reset */
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mt76_clear(dev, MT_WFDMA0_RST,
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MT_WFDMA0_RST_DMASHDL_ALL_RST | MT_WFDMA0_RST_LOGIC_RST);
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mt76_set(dev, MT_WFDMA0_RST,
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MT_WFDMA0_RST_DMASHDL_ALL_RST | MT_WFDMA0_RST_LOGIC_RST);
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/* disable WFDMA0 */
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mt76_clear(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
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MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN |
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MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |
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MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
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usleep_range(1000, 2000);
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mt76_poll(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
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MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);
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mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WA], true);
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/* reset hw queues */
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for (i = 0; i < __MT_TXQ_MAX; i++)
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mt76_queue_tx_cleanup(dev, phy->mt76->q_tx[i], true);
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mt76_queue_reset(dev, dev->mphy.q_tx[i]);
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mt76_for_each_q_rx(&dev->mt76, i) {
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mt76_queue_rx_reset(dev, i);
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}
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for (i = 0; i < __MT_MCUQ_MAX; i++)
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mt76_queue_reset(dev, dev->mt76.q_mcu[i]);
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/* re-init prefetch settings after reset */
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mt76_for_each_q_rx(&dev->mt76, i)
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mt76_queue_reset(dev, &dev->mt76.q_rx[i]);
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/* configure perfetch settings */
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mt7921_dma_prefetch(dev);
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/* reset dma idx */
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mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);
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/* configure delay interrupt */
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mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);
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mt76_set(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_WB_DDONE |
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MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN |
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MT_WFDMA0_GLO_CFG_CLK_GAT_DIS |
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MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
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MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |
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MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
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mt76_set(dev, MT_WFDMA0_GLO_CFG,
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MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
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mt76_set(dev, 0x54000120, BIT(1));
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/* enable interrupts for TX/RX rings */
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mt7921_irq_enable(dev,
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MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
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MT_INT_MCU_CMD);
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}
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void mt7921_tx_token_put(struct mt7921_dev *dev)
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@ -1244,71 +1278,125 @@ void mt7921_tx_token_put(struct mt7921_dev *dev)
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idr_destroy(&dev->token);
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}
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/* system error recovery */
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void mt7921_mac_reset_work(struct work_struct *work)
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static void
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mt7921_vif_connect_iter(void *priv, u8 *mac,
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struct ieee80211_vif *vif)
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{
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struct mt7921_dev *dev;
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struct mt7921_vif *mvif = (struct mt7921_vif *)vif->drv_priv;
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struct mt7921_dev *dev = mvif->phy->dev;
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dev = container_of(work, struct mt7921_dev, reset_work);
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ieee80211_disconnect(vif, true);
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if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_DMA))
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return;
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mt76_connac_mcu_uni_add_dev(&dev->mphy, vif, &mvif->sta.wcid, true);
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mt7921_mcu_set_tx(dev, vif);
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}
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ieee80211_stop_queues(mt76_hw(dev));
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static int
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mt7921_mac_reset(struct mt7921_dev *dev)
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{
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int i, err;
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mt76_connac_free_pending_tx_skbs(&dev->pm, NULL);
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mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
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mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
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set_bit(MT76_RESET, &dev->mphy.state);
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set_bit(MT76_MCU_RESET, &dev->mphy.state);
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wake_up(&dev->mt76.mcu.wait);
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cancel_delayed_work_sync(&dev->mphy.mac_work);
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skb_queue_purge(&dev->mt76.mcu.res_q);
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/* lock/unlock all queues to ensure that no tx is pending */
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mt76_txq_schedule_all(&dev->mphy);
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mt76_worker_disable(&dev->mt76.tx_worker);
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napi_disable(&dev->mt76.napi[0]);
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napi_disable(&dev->mt76.napi[1]);
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napi_disable(&dev->mt76.napi[2]);
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napi_disable(&dev->mt76.napi[MT_RXQ_MAIN]);
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napi_disable(&dev->mt76.napi[MT_RXQ_MCU]);
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napi_disable(&dev->mt76.napi[MT_RXQ_MCU_WA]);
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napi_disable(&dev->mt76.tx_napi);
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mt7921_mutex_acquire(dev);
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mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED);
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mt7921_tx_token_put(dev);
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idr_init(&dev->token);
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if (mt7921_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) {
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mt7921_dma_reset(&dev->phy);
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/* clean up hw queues */
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for (i = 0; i < ARRAY_SIZE(dev->mt76.phy.q_tx); i++)
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mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
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mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT);
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mt7921_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
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for (i = 0; i < ARRAY_SIZE(dev->mt76.q_mcu); i++)
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mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true);
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mt76_for_each_q_rx(&dev->mt76, i)
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mt76_queue_rx_cleanup(dev, &dev->mt76.q_rx[i]);
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mt7921_wfsys_reset(dev);
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mt7921_dma_reset(dev);
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mt76_for_each_q_rx(&dev->mt76, i) {
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mt76_queue_rx_reset(dev, i);
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napi_enable(&dev->mt76.napi[i]);
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napi_schedule(&dev->mt76.napi[i]);
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}
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clear_bit(MT76_MCU_RESET, &dev->mphy.state);
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clear_bit(MT76_RESET, &dev->mphy.state);
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mt76_worker_enable(&dev->mt76.tx_worker);
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napi_enable(&dev->mt76.tx_napi);
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napi_schedule(&dev->mt76.tx_napi);
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mt76_worker_enable(&dev->mt76.tx_worker);
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napi_enable(&dev->mt76.napi[0]);
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napi_schedule(&dev->mt76.napi[0]);
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clear_bit(MT76_MCU_RESET, &dev->mphy.state);
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napi_enable(&dev->mt76.napi[1]);
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napi_schedule(&dev->mt76.napi[1]);
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mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
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mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
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mt7921_irq_enable(dev,
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MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
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MT_INT_MCU_CMD);
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napi_enable(&dev->mt76.napi[2]);
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napi_schedule(&dev->mt76.napi[2]);
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err = mt7921_run_firmware(dev);
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if (err)
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return err;
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ieee80211_wake_queues(mt76_hw(dev));
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err = mt7921_mcu_set_eeprom(dev);
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if (err)
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return err;
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mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE);
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mt7921_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
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mt7921_mac_init(dev);
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return __mt7921_start(&dev->phy);
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}
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mt7921_mutex_release(dev);
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/* system error recovery */
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void mt7921_mac_reset_work(struct work_struct *work)
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{
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struct ieee80211_hw *hw;
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struct mt7921_dev *dev;
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int i;
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ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work,
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MT7921_WATCHDOG_TIME);
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dev = container_of(work, struct mt7921_dev, reset_work);
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hw = mt76_hw(dev);
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dev_err(dev->mt76.dev, "chip reset\n");
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ieee80211_stop_queues(hw);
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cancel_delayed_work_sync(&dev->mphy.mac_work);
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cancel_delayed_work_sync(&dev->pm.ps_work);
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cancel_work_sync(&dev->pm.wake_work);
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mutex_lock(&dev->mt76.mutex);
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for (i = 0; i < 10; i++) {
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if (!mt7921_mac_reset(dev))
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break;
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}
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mutex_unlock(&dev->mt76.mutex);
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if (i == 10)
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dev_err(dev->mt76.dev, "chip reset failed\n");
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ieee80211_wake_queues(hw);
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ieee80211_iterate_active_interfaces(hw,
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IEEE80211_IFACE_ITER_RESUME_ALL,
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mt7921_vif_connect_iter, 0);
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}
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void mt7921_reset(struct mt76_dev *mdev)
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{
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struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
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queue_work(dev->mt76.wq, &dev->reset_work);
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}
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static void
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@ -1505,4 +1593,5 @@ void mt7921_coredump_work(struct work_struct *work)
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}
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dev_coredumpv(dev->mt76.dev, dump, MT76_CONNAC_COREDUMP_SZ,
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GFP_KERNEL);
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mt7921_reset(&dev->mt76);
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}
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@ -952,6 +952,7 @@ int mt7921_mcu_init(struct mt7921_dev *dev)
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.mcu_skb_send_msg = mt7921_mcu_send_message,
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.mcu_parse_response = mt7921_mcu_parse_response,
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.mcu_restart = mt7921_mcu_restart,
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.mcu_reset = mt7921_reset,
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};
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dev->mt76.mcu_ops = &mt7921_mcu_ops;
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@ -1269,6 +1270,7 @@ int mt7921_mcu_drv_pmctrl(struct mt7921_dev *dev)
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if (i == MT7921_DRV_OWN_RETRY_COUNT) {
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dev_err(dev->mt76.dev, "driver own failed\n");
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mt7921_reset(&dev->mt76);
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return -EIO;
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}
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@ -1295,6 +1297,7 @@ int mt7921_mcu_fw_pmctrl(struct mt7921_dev *dev)
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if (i == MT7921_DRV_OWN_RETRY_COUNT) {
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dev_err(dev->mt76.dev, "firmware own failed\n");
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mt7921_reset(&dev->mt76);
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return -EIO;
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}
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@ -151,8 +151,6 @@ struct mt7921_dev {
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struct work_struct init_work;
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struct work_struct reset_work;
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wait_queue_head_t reset_wait;
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u32 reset_state;
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struct list_head sta_poll_list;
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spinlock_t sta_poll_lock;
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@ -283,6 +281,7 @@ mt7921_l1_rmw(struct mt7921_dev *dev, u32 addr, u32 mask, u32 val)
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#define mt7921_l1_set(dev, addr, val) mt7921_l1_rmw(dev, addr, 0, val)
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#define mt7921_l1_clear(dev, addr, val) mt7921_l1_rmw(dev, addr, val, 0)
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void mt7921_mac_init(struct mt7921_dev *dev);
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bool mt7921_mac_wtbl_update(struct mt7921_dev *dev, int idx, u32 mask);
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void mt7921_mac_reset_counters(struct mt7921_phy *phy);
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void mt7921_mac_write_txwi(struct mt7921_dev *dev, __le32 *txwi,
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@ -298,6 +297,7 @@ void mt7921_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
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struct ieee80211_sta *sta);
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void mt7921_mac_work(struct work_struct *work);
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void mt7921_mac_reset_work(struct work_struct *work);
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void mt7921_reset(struct mt76_dev *mdev);
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int mt7921_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
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enum mt76_txq_id qid, struct mt76_wcid *wcid,
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struct ieee80211_sta *sta,
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@ -418,6 +418,10 @@
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#define PCIE_LPCR_HOST_CLR_OWN BIT(1)
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#define PCIE_LPCR_HOST_SET_OWN BIT(0)
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#define MT_WFSYS_SW_RST_B 0x18000140
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#define WFSYS_SW_RST_B BIT(0)
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#define WFSYS_SW_INIT_DONE BIT(4)
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#define MT_CONN_ON_MISC 0x7c0600f0
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#define MT_TOP_MISC2_FW_N9_RDY GENMASK(1, 0)
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