mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-05 18:39:59 +00:00
riscv: Add ptrace vector support
This patch adds ptrace support for riscv vector. The vector registers will be saved in datap pointer of __riscv_v_ext_state. This pointer will be set right after the __riscv_v_ext_state data structure then it will be put in ubuf for ptrace system call to get or set. It will check if the datap got from ubuf is set to the correct address or not when the ptrace system call is trying to set the vector registers. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230605110724.21391-13-andy.chiu@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
parent
cd05483724
commit
0c59922c76
3 changed files with 78 additions and 0 deletions
|
@ -94,6 +94,13 @@ struct __riscv_v_ext_state {
|
|||
*/
|
||||
};
|
||||
|
||||
/*
|
||||
* According to spec: The number of bits in a single vector register,
|
||||
* VLEN >= ELEN, which must be a power of 2, and must be no greater than
|
||||
* 2^16 = 65536bits = 8192bytes
|
||||
*/
|
||||
#define RISCV_MAX_VLENB (8192)
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _UAPI_ASM_RISCV_PTRACE_H */
|
||||
|
|
|
@ -7,6 +7,7 @@
|
|||
* Copied from arch/tile/kernel/ptrace.c
|
||||
*/
|
||||
|
||||
#include <asm/vector.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/syscall.h>
|
||||
#include <asm/thread_info.h>
|
||||
|
@ -24,6 +25,9 @@ enum riscv_regset {
|
|||
#ifdef CONFIG_FPU
|
||||
REGSET_F,
|
||||
#endif
|
||||
#ifdef CONFIG_RISCV_ISA_V
|
||||
REGSET_V,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int riscv_gpr_get(struct task_struct *target,
|
||||
|
@ -80,6 +84,61 @@ static int riscv_fpr_set(struct task_struct *target,
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RISCV_ISA_V
|
||||
static int riscv_vr_get(struct task_struct *target,
|
||||
const struct user_regset *regset,
|
||||
struct membuf to)
|
||||
{
|
||||
struct __riscv_v_ext_state *vstate = &target->thread.vstate;
|
||||
|
||||
if (!riscv_v_vstate_query(task_pt_regs(target)))
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* Ensure the vector registers have been saved to the memory before
|
||||
* copying them to membuf.
|
||||
*/
|
||||
if (target == current)
|
||||
riscv_v_vstate_save(current, task_pt_regs(current));
|
||||
|
||||
/* Copy vector header from vstate. */
|
||||
membuf_write(&to, vstate, offsetof(struct __riscv_v_ext_state, datap));
|
||||
membuf_zero(&to, sizeof(vstate->datap));
|
||||
|
||||
/* Copy all the vector registers from vstate. */
|
||||
return membuf_write(&to, vstate->datap, riscv_v_vsize);
|
||||
}
|
||||
|
||||
static int riscv_vr_set(struct task_struct *target,
|
||||
const struct user_regset *regset,
|
||||
unsigned int pos, unsigned int count,
|
||||
const void *kbuf, const void __user *ubuf)
|
||||
{
|
||||
int ret, size;
|
||||
struct __riscv_v_ext_state *vstate = &target->thread.vstate;
|
||||
|
||||
if (!riscv_v_vstate_query(task_pt_regs(target)))
|
||||
return -EINVAL;
|
||||
|
||||
/* Copy rest of the vstate except datap */
|
||||
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate, 0,
|
||||
offsetof(struct __riscv_v_ext_state, datap));
|
||||
if (unlikely(ret))
|
||||
return ret;
|
||||
|
||||
/* Skip copy datap. */
|
||||
size = sizeof(vstate->datap);
|
||||
count -= size;
|
||||
ubuf += size;
|
||||
|
||||
/* Copy all the vector registers. */
|
||||
pos = 0;
|
||||
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate->datap,
|
||||
0, riscv_v_vsize);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct user_regset riscv_user_regset[] = {
|
||||
[REGSET_X] = {
|
||||
.core_note_type = NT_PRSTATUS,
|
||||
|
@ -99,6 +158,17 @@ static const struct user_regset riscv_user_regset[] = {
|
|||
.set = riscv_fpr_set,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_RISCV_ISA_V
|
||||
[REGSET_V] = {
|
||||
.core_note_type = NT_RISCV_VECTOR,
|
||||
.align = 16,
|
||||
.n = ((32 * RISCV_MAX_VLENB) +
|
||||
sizeof(struct __riscv_v_ext_state)) / sizeof(__u32),
|
||||
.size = sizeof(__u32),
|
||||
.regset_get = riscv_vr_get,
|
||||
.set = riscv_vr_set,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static const struct user_regset_view riscv_user_native_view = {
|
||||
|
|
|
@ -440,6 +440,7 @@ typedef struct elf64_shdr {
|
|||
#define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */
|
||||
#define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode */
|
||||
#define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */
|
||||
#define NT_RISCV_VECTOR 0x900 /* RISC-V vector registers */
|
||||
#define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */
|
||||
#define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */
|
||||
#define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */
|
||||
|
|
Loading…
Reference in a new issue