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drm/amdgpu: export gfxhub sw_init into gmc
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1e4eccdaf2
commit
0c8c0847cc
3 changed files with 17 additions and 12 deletions
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@ -337,19 +337,8 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
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}
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static int gfxhub_v1_0_early_init(void *handle)
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void gfxhub_v1_0_init(struct amdgpu_device *adev)
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{
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return 0;
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}
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static int gfxhub_v1_0_late_init(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_sw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
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hub->ctx0_ptb_addr_lo32 =
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@ -368,7 +357,20 @@ static int gfxhub_v1_0_sw_init(void *handle)
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SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
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hub->vm_l2_pro_fault_cntl =
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SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
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}
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static int gfxhub_v1_0_early_init(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_late_init(void *handle)
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{
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return 0;
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}
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static int gfxhub_v1_0_sw_init(void *handle)
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{
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return 0;
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}
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@ -28,6 +28,7 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev);
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void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev);
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void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
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bool value);
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void gfxhub_v1_0_init(struct amdgpu_device *adev);
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u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev);
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extern const struct amd_ip_funcs gfxhub_v1_0_ip_funcs;
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extern const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block;
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@ -532,6 +532,8 @@ static int gmc_v9_0_sw_init(void *handle)
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int dma_bits;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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gfxhub_v1_0_init(adev);
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spin_lock_init(&adev->mc.invalidate_lock);
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if (adev->flags & AMD_IS_APU) {
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