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Merge branch 'net-next-dsa-mt7530-add-support-for-MT7531'
Landen Chao says:
====================
net-next: dsa: mt7530: add support for MT7531
This patch series adds support for MT7531.
MT7531 is the next generation of MT7530 which could be found on Mediatek
router platforms such as MT7622 or MT7629.
It is also a 7-ports switch with 5 giga embedded phys, 2 cpu ports, and
the same MAC logic of MT7530. Cpu port 6 only supports SGMII interface.
Cpu port 5 supports either RGMII or SGMII in different HW SKU, but cannot
be muxed to PHY of port 0/4 like mt7530. Due to support for SGMII
interface, pll, and pad setting are different from MT7530.
MT7531 SGMII interface can be configured in following mode:
- 'SGMII AN mode' with in-band negotiation capability
which is compatible with PHY_INTERFACE_MODE_SGMII.
- 'SGMII force mode' without in-band negotiation
which is compatible with 10B/8B encoding of
PHY_INTERFACE_MODE_1000BASEX with fixed full-duplex and fixed pause.
- 2.5 times faster clocked 'SGMII force mode' without in-band negotiation
which is compatible with 10B/8B encoding of
PHY_INTERFACE_MODE_2500BASEX with fixed full-duplex and fixed pause.
v4 -> v5
- Add fixed-link node to dsa cpu port in dts file by suggestion of
Vladimir Oltean.
v3 -> v4
- Adjust the coding style by suggestion of Jakub Kicinski.
Remove unnecessary jumping label, merge continuous numeric 'switch
cases' into one line, and keep the variables longest to shortest
(reverse xmas tree).
v2 -> v3
- Keep the same setup logic of mt7530/mt7621 because these series of
patches is for adding mt7531 hardware.
- Do not adjust rgmii delay when vendor phy driver presents in order to
prevent double adjustment by suggestion of Andrew Lunn.
- Remove redundant 'Example 4' from dt-bindings by suggestion of
Rob Herring.
- Fix typo.
v1 -> v2
- change phylink_validate callback function to support full-duplex
gigabit only to match hardware capability.
- add description of SGMII interface.
- configure mt7531 cpu port in fastest speed by default.
- parse SGMII control word for in-band negotiation mode.
- configure RGMII delay based on phy.rst.
- Rename the definition in the header file to avoid potential conflicts.
- Add wrapper function for mdio read/write to support both C22 and C45.
- correct fixed-link speed of 2500base-x in dts.
- add MT7531 port mirror setting.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
0ca6d8b7d6
6 changed files with 1458 additions and 107 deletions
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@ -5,6 +5,7 @@ Required properties:
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- compatible: may be compatible = "mediatek,mt7530"
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or compatible = "mediatek,mt7621"
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or compatible = "mediatek,mt7531"
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- #address-cells: Must be 1.
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- #size-cells: Must be 0.
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- mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
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@ -32,10 +33,14 @@ Required properties for the child nodes within ports container:
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- reg: Port address described must be 6 for CPU port and from 0 to 5 for
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user ports.
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- phy-mode: String, must be either "trgmii" or "rgmii" for port labeled
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"cpu".
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- phy-mode: String, the following values are acceptable for port labeled
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"cpu":
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If compatible mediatek,mt7530 or mediatek,mt7621 is set,
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must be either "trgmii" or "rgmii"
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If compatible mediatek,mt7531 is set,
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must be either "sgmii", "1000base-x" or "2500base-x"
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Port 5 of the switch is muxed between:
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Port 5 of mt7530 and mt7621 switch is muxed between:
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1. GMAC5: GMAC5 can interface with another external MAC or PHY.
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2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
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of the SOC. Used in many setups where port 0/4 becomes the WAN port.
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@ -143,6 +143,56 @@ fixed-link {
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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switch@0 {
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compatible = "mediatek,mt7531";
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reg = <0>;
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reset-gpios = <&pio 54 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "wan";
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};
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port@1 {
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reg = <1>;
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label = "lan0";
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};
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port@2 {
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reg = <2>;
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label = "lan1";
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};
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port@3 {
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reg = <3>;
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label = "lan2";
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};
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port@4 {
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reg = <4>;
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label = "lan3";
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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};
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@ -105,20 +105,71 @@ ð {
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pinctrl-0 = <ð_pins>;
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status = "okay";
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gmac1: mac@1 {
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-handle = <&phy5>;
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reg = <0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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phy5: ethernet-phy@5 {
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reg = <5>;
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phy-mode = "sgmii";
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switch@0 {
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compatible = "mediatek,mt7531";
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reg = <0>;
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reset-gpios = <&pio 54 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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};
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port@4 {
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reg = <4>;
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label = "wan";
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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};
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@ -33,12 +33,12 @@ config NET_DSA_LANTIQ_GSWIP
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the xrx200 / VR9 SoC.
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config NET_DSA_MT7530
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tristate "Mediatek MT7530 Ethernet switch support"
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tristate "MediaTek MT753x and MT7621 Ethernet switch support"
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depends on NET_DSA
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select NET_DSA_TAG_MTK
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help
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This enables support for the Mediatek MT7530 Ethernet switch
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chip.
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This enables support for the MediaTek MT7530, MT7531, and MT7621
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Ethernet switch chips.
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config NET_DSA_MV88E6060
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tristate "Marvell 88E6060 ethernet switch chip support"
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File diff suppressed because it is too large
Load diff
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@ -11,9 +11,10 @@
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#define MT7530_NUM_FDB_RECORDS 2048
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#define MT7530_ALL_MEMBERS 0xff
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enum {
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enum mt753x_id {
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ID_MT7530 = 0,
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ID_MT7621 = 1,
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ID_MT7531 = 2,
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};
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#define NUM_TRGMII_CTRL 5
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@ -41,6 +42,33 @@ enum {
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#define MIRROR_PORT(x) ((x) & 0x7)
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#define MIRROR_MASK 0x7
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/* Registers for CPU forward control */
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#define MT7531_CFC 0x4
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#define MT7531_MIRROR_EN BIT(19)
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#define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
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#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
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#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
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#define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
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#define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \
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MT7531_CFC : MT7530_MFC)
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#define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \
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MT7531_MIRROR_EN : MIRROR_EN)
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#define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \
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MT7531_MIRROR_MASK : MIRROR_MASK)
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/* Registers for BPDU and PAE frame control*/
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#define MT753X_BPC 0x24
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#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
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enum mt753x_bpdu_port_fw {
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MT753X_BPDU_FOLLOW_MFC,
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MT753X_BPDU_CPU_EXCLUDE = 4,
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MT753X_BPDU_CPU_INCLUDE = 5,
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MT753X_BPDU_CPU_ONLY = 6,
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MT753X_BPDU_DROP = 7,
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};
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/* Registers for address table access */
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#define MT7530_ATA1 0x74
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#define STATIC_EMP 0
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@ -220,10 +248,30 @@ enum mt7530_vlan_port_attr {
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#define PMCR_FORCE_LNK BIT(0)
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#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
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PMCR_FORCE_SPEED_1000)
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#define MT7531_FORCE_LNK BIT(31)
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#define MT7531_FORCE_SPD BIT(30)
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#define MT7531_FORCE_DPX BIT(29)
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#define MT7531_FORCE_RX_FC BIT(28)
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#define MT7531_FORCE_TX_FC BIT(27)
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#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
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MT7531_FORCE_SPD | \
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MT7531_FORCE_DPX | \
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MT7531_FORCE_RX_FC | \
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MT7531_FORCE_TX_FC)
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#define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \
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MT7531_FORCE_MODE : \
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PMCR_FORCE_MODE)
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#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
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PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
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PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
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PMCR_FORCE_FDX | PMCR_FORCE_LNK)
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#define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \
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PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
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PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
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PMCR_TX_EN | PMCR_RX_EN | \
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PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
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PMCR_FORCE_SPEED_1000 | \
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PMCR_FORCE_FDX | PMCR_FORCE_LNK)
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#define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
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#define PMSR_EEE1G BIT(7)
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@ -237,6 +285,10 @@ enum mt7530_vlan_port_attr {
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#define PMSR_DPX BIT(1)
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#define PMSR_LINK BIT(0)
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/* Register for port debug count */
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#define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
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#define MT7531_DIS_CLR BIT(31)
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/* Register for MIB */
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#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
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#define MT7530_MIB_CCR 0x4fe0
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@ -254,12 +306,118 @@ enum mt7530_vlan_port_attr {
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CCR_RX_OCT_CNT_BAD | \
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CCR_TX_OCT_CNT_GOOD | \
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CCR_TX_OCT_CNT_BAD)
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/* MT7531 SGMII register group */
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#define MT7531_SGMII_REG_BASE 0x5000
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#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
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((p) - 5) * 0x1000 + (r))
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/* Register forSGMII PCS_CONTROL_1 */
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#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00)
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#define MT7531_SGMII_LINK_STATUS BIT(18)
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#define MT7531_SGMII_AN_ENABLE BIT(12)
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#define MT7531_SGMII_AN_RESTART BIT(9)
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/* Register for SGMII PCS_SPPED_ABILITY */
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#define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08)
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#define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0)
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#define MT7531_SGMII_TX_CONFIG BIT(0)
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/* Register for SGMII_MODE */
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#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20)
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#define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8)
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#define MT7531_SGMII_IF_MODE_MASK GENMASK(5, 1)
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#define MT7531_SGMII_FORCE_DUPLEX BIT(4)
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#define MT7531_SGMII_FORCE_SPEED_MASK GENMASK(3, 2)
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#define MT7531_SGMII_FORCE_SPEED_1000 BIT(3)
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#define MT7531_SGMII_FORCE_SPEED_100 BIT(2)
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#define MT7531_SGMII_FORCE_SPEED_10 0
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#define MT7531_SGMII_SPEED_DUPLEX_AN BIT(1)
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enum mt7531_sgmii_force_duplex {
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MT7531_SGMII_FORCE_FULL_DUPLEX = 0,
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MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10,
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};
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/* Fields of QPHY_PWR_STATE_CTRL */
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#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8)
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#define MT7531_SGMII_PHYA_PWD BIT(4)
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/* Values of SGMII SPEED */
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#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128)
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#define MT7531_RG_TPHY_SPEED_MASK (BIT(2) | BIT(3))
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#define MT7531_RG_TPHY_SPEED_1_25G 0x0
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#define MT7531_RG_TPHY_SPEED_3_125G BIT(2)
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/* Register for system reset */
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#define MT7530_SYS_CTRL 0x7000
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#define SYS_CTRL_PHY_RST BIT(2)
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#define SYS_CTRL_SW_RST BIT(1)
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#define SYS_CTRL_REG_RST BIT(0)
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/* Register for PHY Indirect Access Control */
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#define MT7531_PHY_IAC 0x701C
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#define MT7531_PHY_ACS_ST BIT(31)
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#define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
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#define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
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#define MT7531_MDIO_CMD_MASK (0x3 << 18)
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#define MT7531_MDIO_ST_MASK (0x3 << 16)
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#define MT7531_MDIO_RW_DATA_MASK (0xffff)
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#define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
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#define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
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#define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
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#define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
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#define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
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enum mt7531_phy_iac_cmd {
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MT7531_MDIO_ADDR = 0,
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MT7531_MDIO_WRITE = 1,
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MT7531_MDIO_READ = 2,
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MT7531_MDIO_READ_CL45 = 3,
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};
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/* MDIO_ST: MDIO start field */
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enum mt7531_mdio_st {
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MT7531_MDIO_ST_CL45 = 0,
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MT7531_MDIO_ST_CL22 = 1,
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};
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#define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
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MT7531_MDIO_CMD(MT7531_MDIO_READ))
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#define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
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MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
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#define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
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MT7531_MDIO_CMD(MT7531_MDIO_ADDR))
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#define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
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MT7531_MDIO_CMD(MT7531_MDIO_READ))
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#define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
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MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
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/* Register for RGMII clock phase */
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#define MT7531_CLKGEN_CTRL 0x7500
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#define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
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#define CLK_SKEW_OUT_MASK GENMASK(9, 8)
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#define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
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#define CLK_SKEW_IN_MASK GENMASK(7, 6)
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#define RXCLK_NO_DELAY BIT(5)
|
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#define TXCLK_NO_REVERSE BIT(4)
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#define GP_MODE(x) (((x) & 0x3) << 1)
|
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#define GP_MODE_MASK GENMASK(2, 1)
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#define GP_CLK_EN BIT(0)
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|
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enum mt7531_gp_mode {
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MT7531_GP_MODE_RGMII = 0,
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MT7531_GP_MODE_MII = 1,
|
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MT7531_GP_MODE_REV_MII = 2
|
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};
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enum mt7531_clk_skew {
|
||||
MT7531_CLK_SKEW_NO_CHG = 0,
|
||||
MT7531_CLK_SKEW_DLY_100PPS = 1,
|
||||
MT7531_CLK_SKEW_DLY_200PPS = 2,
|
||||
MT7531_CLK_SKEW_REVERSE = 3,
|
||||
};
|
||||
|
||||
/* Register for hw trap status */
|
||||
#define MT7530_HWTRAP 0x7800
|
||||
#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
|
||||
|
|
@ -267,6 +425,16 @@ enum mt7530_vlan_port_attr {
|
|||
#define HWTRAP_XTAL_40MHZ (BIT(10))
|
||||
#define HWTRAP_XTAL_20MHZ (BIT(9))
|
||||
|
||||
#define MT7531_HWTRAP 0x7800
|
||||
#define HWTRAP_XTAL_FSEL_MASK BIT(7)
|
||||
#define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
|
||||
#define HWTRAP_XTAL_FSEL_40MHZ 0
|
||||
/* Unique fields of (M)HWSTRAP for MT7531 */
|
||||
#define XTAL_FSEL_S 7
|
||||
#define XTAL_FSEL_M BIT(7)
|
||||
#define PHY_EN BIT(6)
|
||||
#define CHG_STRAP BIT(8)
|
||||
|
||||
/* Register for hw trap modification */
|
||||
#define MT7530_MHWTRAP 0x7804
|
||||
#define MHWTRAP_PHY0_SEL BIT(20)
|
||||
|
|
@ -281,14 +449,37 @@ enum mt7530_vlan_port_attr {
|
|||
#define MT7530_TOP_SIG_CTRL 0x7808
|
||||
#define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
|
||||
|
||||
#define MT7531_TOP_SIG_SR 0x780c
|
||||
#define PAD_DUAL_SGMII_EN BIT(1)
|
||||
#define PAD_MCM_SMI_EN BIT(0)
|
||||
|
||||
#define MT7530_IO_DRV_CR 0x7810
|
||||
#define P5_IO_CLK_DRV(x) ((x) & 0x3)
|
||||
#define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
|
||||
|
||||
#define MT7531_CHIP_REV 0x781C
|
||||
|
||||
#define MT7531_PLLGP_EN 0x7820
|
||||
#define EN_COREPLL BIT(2)
|
||||
#define SW_CLKSW BIT(1)
|
||||
#define SW_PLLGP BIT(0)
|
||||
|
||||
#define MT7530_P6ECR 0x7830
|
||||
#define P6_INTF_MODE_MASK 0x3
|
||||
#define P6_INTF_MODE(x) ((x) & 0x3)
|
||||
|
||||
#define MT7531_PLLGP_CR0 0x78a8
|
||||
#define RG_COREPLL_EN BIT(22)
|
||||
#define RG_COREPLL_POSDIV_S 23
|
||||
#define RG_COREPLL_POSDIV_M 0x3800000
|
||||
#define RG_COREPLL_SDM_PCW_S 1
|
||||
#define RG_COREPLL_SDM_PCW_M 0x3ffffe
|
||||
#define RG_COREPLL_SDM_PCW_CHG BIT(0)
|
||||
|
||||
/* Registers for RGMII and SGMII PLL clock */
|
||||
#define MT7531_ANA_PLLGP_CR2 0x78b0
|
||||
#define MT7531_ANA_PLLGP_CR5 0x78bc
|
||||
|
||||
/* Registers for TRGMII on the both side */
|
||||
#define MT7530_TRGMII_RCK_CTRL 0x7a00
|
||||
#define RX_RST BIT(31)
|
||||
|
|
@ -327,10 +518,25 @@ enum mt7530_vlan_port_attr {
|
|||
#define MT7530_P5RGMIITXCR 0x7b04
|
||||
#define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
|
||||
|
||||
/* Registers for GPIO mode */
|
||||
#define MT7531_GPIO_MODE0 0x7c0c
|
||||
#define MT7531_GPIO0_MASK GENMASK(3, 0)
|
||||
#define MT7531_GPIO0_INTERRUPT 1
|
||||
|
||||
#define MT7531_GPIO_MODE1 0x7c10
|
||||
#define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12)
|
||||
#define MT7531_EXT_P_MDC_11 (2 << 12)
|
||||
#define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16)
|
||||
#define MT7531_EXT_P_MDIO_12 (2 << 16)
|
||||
|
||||
#define MT7530_CREV 0x7ffc
|
||||
#define CHIP_NAME_SHIFT 16
|
||||
#define MT7530_ID 0x7530
|
||||
|
||||
#define MT7531_CREV 0x781C
|
||||
#define CHIP_REV_M 0x0f
|
||||
#define MT7531_ID 0x7531
|
||||
|
||||
/* Registers for core PLL access through mmd indirect */
|
||||
#define CORE_PLL_GROUP2 0x401
|
||||
#define RG_SYSPLL_EN_NORMAL BIT(15)
|
||||
|
|
@ -347,6 +553,10 @@ enum mt7530_vlan_port_attr {
|
|||
#define RG_SYSPLL_DDSFBK_EN BIT(12)
|
||||
#define RG_SYSPLL_BIAS_EN BIT(11)
|
||||
#define RG_SYSPLL_BIAS_LPF_EN BIT(10)
|
||||
#define MT7531_PHY_PLL_OFF BIT(5)
|
||||
#define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
|
||||
|
||||
#define MT753X_CTRL_PHY_ADDR 0
|
||||
|
||||
#define CORE_PLL_GROUP5 0x404
|
||||
#define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
|
||||
|
|
@ -425,6 +635,7 @@ enum p5_interface_select {
|
|||
P5_INTF_SEL_PHY_P0,
|
||||
P5_INTF_SEL_PHY_P4,
|
||||
P5_INTF_SEL_GMAC5,
|
||||
P5_INTF_SEL_GMAC5_SGMII,
|
||||
};
|
||||
|
||||
static const char *p5_intf_modes(unsigned int p5_interface)
|
||||
|
|
@ -438,11 +649,56 @@ static const char *p5_intf_modes(unsigned int p5_interface)
|
|||
return "PHY P4";
|
||||
case P5_INTF_SEL_GMAC5:
|
||||
return "GMAC5";
|
||||
case P5_INTF_SEL_GMAC5_SGMII:
|
||||
return "GMAC5_SGMII";
|
||||
default:
|
||||
return "unknown";
|
||||
}
|
||||
}
|
||||
|
||||
/* struct mt753x_info - This is the main data structure for holding the specific
|
||||
* part for each supported device
|
||||
* @sw_setup: Holding the handler to a device initialization
|
||||
* @phy_read: Holding the way reading PHY port
|
||||
* @phy_write: Holding the way writing PHY port
|
||||
* @pad_setup: Holding the way setting up the bus pad for a certain
|
||||
* MAC port
|
||||
* @phy_mode_supported: Check if the PHY type is being supported on a certain
|
||||
* port
|
||||
* @mac_port_validate: Holding the way to set addition validate type for a
|
||||
* certan MAC port
|
||||
* @mac_port_get_state: Holding the way getting the MAC/PCS state for a certain
|
||||
* MAC port
|
||||
* @mac_port_config: Holding the way setting up the PHY attribute to a
|
||||
* certain MAC port
|
||||
* @mac_pcs_an_restart Holding the way restarting PCS autonegotiation for a
|
||||
* certain MAC port
|
||||
* @mac_pcs_link_up: Holding the way setting up the PHY attribute to the pcs
|
||||
* of the certain MAC port
|
||||
*/
|
||||
struct mt753x_info {
|
||||
enum mt753x_id id;
|
||||
|
||||
int (*sw_setup)(struct dsa_switch *ds);
|
||||
int (*phy_read)(struct dsa_switch *ds, int port, int regnum);
|
||||
int (*phy_write)(struct dsa_switch *ds, int port, int regnum, u16 val);
|
||||
int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);
|
||||
int (*cpu_port_config)(struct dsa_switch *ds, int port);
|
||||
bool (*phy_mode_supported)(struct dsa_switch *ds, int port,
|
||||
const struct phylink_link_state *state);
|
||||
void (*mac_port_validate)(struct dsa_switch *ds, int port,
|
||||
unsigned long *supported);
|
||||
int (*mac_port_get_state)(struct dsa_switch *ds, int port,
|
||||
struct phylink_link_state *state);
|
||||
int (*mac_port_config)(struct dsa_switch *ds, int port,
|
||||
unsigned int mode,
|
||||
phy_interface_t interface);
|
||||
void (*mac_pcs_an_restart)(struct dsa_switch *ds, int port);
|
||||
void (*mac_pcs_link_up)(struct dsa_switch *ds, int port,
|
||||
unsigned int mode, phy_interface_t interface,
|
||||
int speed, int duplex);
|
||||
};
|
||||
|
||||
/* struct mt7530_priv - This is the main data structure for holding the state
|
||||
* of the driver
|
||||
* @dev: The device pointer
|
||||
|
|
@ -468,6 +724,7 @@ struct mt7530_priv {
|
|||
struct regulator *core_pwr;
|
||||
struct regulator *io_pwr;
|
||||
struct gpio_desc *reset;
|
||||
const struct mt753x_info *info;
|
||||
unsigned int id;
|
||||
bool mcm;
|
||||
phy_interface_t p6_interface;
|
||||
|
|
|
|||
Loading…
Reference in a new issue