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watchdog: octeon-wdt: Add support for cn68XX SOCs.
Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Carlos Munoz <cmunoz@caviumnetworks.com> Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Cc: linux-mips@linux-mips.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17213/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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381cec022e
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1 changed files with 35 additions and 13 deletions
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@ -69,6 +69,9 @@
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-boot-vector.h>
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#include <asm/octeon/cvmx-ciu2-defs.h>
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static int divisor;
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/* The count needed to achieve timeout_sec. */
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static unsigned int timeout_cnt;
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@ -227,10 +230,10 @@ void octeon_wdt_nmi_stage3(u64 reg[32])
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u64 cp0_epc = read_c0_epc();
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/* Delay so output from all cores output is not jumbled together. */
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__delay(100000000ull * coreid);
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udelay(85000 * coreid);
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octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x");
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octeon_wdt_write_hex(coreid, 1);
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octeon_wdt_write_hex(coreid, 2);
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octeon_wdt_write_string(" ***\r\n");
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for (i = 0; i < 32; i++) {
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octeon_wdt_write_string("\t");
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@ -253,11 +256,28 @@ void octeon_wdt_nmi_stage3(u64 reg[32])
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octeon_wdt_write_hex(cp0_cause, 16);
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octeon_wdt_write_string("\r\n");
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octeon_wdt_write_string("\tsum0\t0x");
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);
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octeon_wdt_write_string("\ten0\t0x");
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);
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octeon_wdt_write_string("\r\n");
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/* The CIU register is different for each Octeon model. */
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if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
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octeon_wdt_write_string("\tsrc_wd\t0x");
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16);
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octeon_wdt_write_string("\ten_wd\t0x");
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16);
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octeon_wdt_write_string("\r\n");
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octeon_wdt_write_string("\tsrc_rml\t0x");
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16);
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octeon_wdt_write_string("\ten_rml\t0x");
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16);
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octeon_wdt_write_string("\r\n");
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octeon_wdt_write_string("\tsum\t0x");
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16);
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octeon_wdt_write_string("\r\n");
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} else if (!octeon_has_feature(OCTEON_FEATURE_CIU3)) {
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octeon_wdt_write_string("\tsum0\t0x");
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);
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octeon_wdt_write_string("\ten0\t0x");
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octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);
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octeon_wdt_write_string("\r\n");
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}
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octeon_wdt_write_string("*** Chip soft reset soon ***\r\n");
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}
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@ -366,7 +386,7 @@ static void octeon_wdt_calc_parameters(int t)
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countdown_reset = periods > 2 ? periods - 2 : 0;
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heartbeat = t;
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timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * timeout_sec) >> 8;
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timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * timeout_sec) >> 8;
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}
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static int octeon_wdt_set_timeout(struct watchdog_device *wdog,
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@ -437,9 +457,7 @@ static enum cpuhp_state octeon_wdt_online;
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*/
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static int __init octeon_wdt_init(void)
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{
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int i;
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int ret;
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u64 *ptr;
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octeon_wdt_bootvector = cvmx_boot_vector_get();
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if (!octeon_wdt_bootvector) {
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@ -447,10 +465,15 @@ static int __init octeon_wdt_init(void)
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return -ENOMEM;
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}
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if (OCTEON_IS_MODEL(OCTEON_CN68XX))
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divisor = 0x200;
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else
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divisor = 0x100;
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/*
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* Watchdog time expiration length = The 16 bits of LEN
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* represent the most significant bits of a 24 bit decrementer
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* that decrements every 256 cycles.
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* that decrements every divisor cycle.
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*
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* Try for a timeout of 5 sec, if that fails a smaller number
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* of even seconds,
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@ -458,8 +481,7 @@ static int __init octeon_wdt_init(void)
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max_timeout_sec = 6;
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do {
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max_timeout_sec--;
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timeout_cnt = ((octeon_get_io_clock_rate() >> 8) *
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max_timeout_sec) >> 8;
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timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * max_timeout_sec) >> 8;
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} while (timeout_cnt > 65535);
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BUG_ON(timeout_cnt == 0);
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