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drm/amdgpu: Implement irq interfaces for CGS
This implements the irq src registrar. Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
97cb7f6e6c
commit
0cf3be2178
5 changed files with 84 additions and 6 deletions
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@ -290,26 +290,95 @@ static int amdgpu_cgs_set_camera_voltages(void *cgs_device, uint32_t mask,
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return -EPERM;
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}
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struct cgs_irq_params {
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unsigned src_id;
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cgs_irq_source_set_func_t set;
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cgs_irq_handler_func_t handler;
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void *private_data;
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};
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static int cgs_set_irq_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *src,
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unsigned type,
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enum amdgpu_interrupt_state state)
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{
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struct cgs_irq_params *irq_params =
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(struct cgs_irq_params *)src->data;
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if (!irq_params)
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return -EINVAL;
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if (!irq_params->set)
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return -EINVAL;
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return irq_params->set(irq_params->private_data,
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irq_params->src_id,
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type,
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(int)state);
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}
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static int cgs_process_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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struct cgs_irq_params *irq_params =
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(struct cgs_irq_params *)source->data;
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if (!irq_params)
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return -EINVAL;
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if (!irq_params->handler)
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return -EINVAL;
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return irq_params->handler(irq_params->private_data,
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irq_params->src_id,
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entry->iv_entry);
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}
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static const struct amdgpu_irq_src_funcs cgs_irq_funcs = {
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.set = cgs_set_irq_state,
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.process = cgs_process_irq,
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};
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static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id,
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unsigned num_types,
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cgs_irq_source_set_func_t set,
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cgs_irq_handler_func_t handler,
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void *private_data)
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{
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/* TODO */
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return 0;
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CGS_FUNC_ADEV;
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int ret = 0;
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struct cgs_irq_params *irq_params;
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struct amdgpu_irq_src *source =
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kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
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if (!source)
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return -ENOMEM;
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irq_params =
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kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
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if (!irq_params) {
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kfree(source);
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return -ENOMEM;
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}
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source->num_types = num_types;
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source->funcs = &cgs_irq_funcs;
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irq_params->src_id = src_id;
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irq_params->set = set;
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irq_params->handler = handler;
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irq_params->private_data = private_data;
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source->data = (void *)irq_params;
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ret = amdgpu_irq_add_id(adev, src_id, source);
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if (ret) {
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kfree(irq_params);
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kfree(source);
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}
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return ret;
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}
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static int amdgpu_cgs_irq_get(void *cgs_device, unsigned src_id, unsigned type)
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{
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/* TODO */
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return 0;
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CGS_FUNC_ADEV;
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return amdgpu_irq_get(adev, adev->irq.sources[src_id], type);
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}
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static int amdgpu_cgs_irq_put(void *cgs_device, unsigned src_id, unsigned type)
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{
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/* TODO */
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return 0;
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CGS_FUNC_ADEV;
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return amdgpu_irq_put(adev, adev->irq.sources[src_id], type);
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}
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static const struct cgs_ops amdgpu_cgs_ops = {
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@ -206,6 +206,8 @@ int amdgpu_ih_process(struct amdgpu_device *adev)
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amdgpu_amdkfd_interrupt(adev,
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(const void *) &adev->irq.ih.ring[ring_index]);
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entry.iv_entry = (const uint32_t *)
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&adev->irq.ih.ring[ring_index];
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amdgpu_ih_decode_iv(adev, &entry);
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adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
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@ -52,6 +52,7 @@ struct amdgpu_iv_entry {
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unsigned ring_id;
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unsigned vm_id;
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unsigned pas_id;
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const uint32_t *iv_entry;
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};
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int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
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@ -272,6 +272,11 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
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kfree(src->enabled_types);
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src->enabled_types = NULL;
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if (src->data) {
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kfree(src->data);
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kfree(src);
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adev->irq.sources[i] = NULL;
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}
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}
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}
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@ -40,6 +40,7 @@ struct amdgpu_irq_src {
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unsigned num_types;
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atomic_t *enabled_types;
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const struct amdgpu_irq_src_funcs *funcs;
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void *data;
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};
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/* provided by interrupt generating IP blocks */
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