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phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_b
Since now there is support for configuring the HS Rate B mode properly, let's move the register setting to tbls_hs_b struct for all SoCs. This allows the PHY to be configured in Rate A initially and then in Rate B if requested by the UFS driver. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-7-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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1 changed files with 32 additions and 5 deletions
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@ -219,8 +219,9 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
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QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
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};
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/* Rate B */
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static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = {
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
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};
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@ -296,8 +297,9 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = {
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
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};
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/* Rate B */
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static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = {
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
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};
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@ -362,8 +364,9 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
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};
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/* Rate B */
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static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
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};
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@ -411,7 +414,6 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
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QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
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};
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static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
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@ -449,8 +451,9 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
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QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
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QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
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QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
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};
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/* Rate B */
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static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = {
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QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
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};
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@ -684,6 +687,10 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
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.pcs = sm8350_ufsphy_pcs,
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.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
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},
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.tbls_hs_b = {
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.serdes = sm8350_ufsphy_hs_b_serdes,
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.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
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},
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.clk_list = sdm845_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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@ -704,6 +711,10 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
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.pcs = sdm845_ufsphy_pcs,
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.pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
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},
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.tbls_hs_b = {
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.serdes = sdm845_ufsphy_hs_b_serdes,
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.serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
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},
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.clk_list = sdm845_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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@ -728,6 +739,10 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
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.pcs = sm6115_ufsphy_pcs,
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.pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
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},
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.tbls_hs_b = {
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.serdes = sm6115_ufsphy_hs_b_serdes,
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.serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes),
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},
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.clk_list = sdm845_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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@ -750,6 +765,10 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
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.pcs = sm8150_ufsphy_pcs,
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.pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
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},
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.tbls_hs_b = {
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.serdes = sm8150_ufsphy_hs_b_serdes,
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.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
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},
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.clk_list = sdm845_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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@ -770,6 +789,10 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
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.pcs = sm8350_ufsphy_pcs,
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.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
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},
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.tbls_hs_b = {
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.serdes = sm8350_ufsphy_hs_b_serdes,
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.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
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},
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.clk_list = sdm845_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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@ -790,6 +813,10 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
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.pcs = sm8350_ufsphy_pcs,
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.pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
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},
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.tbls_hs_b = {
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.serdes = sm8350_ufsphy_hs_b_serdes,
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.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
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},
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.clk_list = sm8450_ufs_phy_clk_l,
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.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
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.vreg_list = qmp_phy_vreg_l,
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