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clk: meson: meson8b: Fix the polarity of the RESET_N lines
CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST and
CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE are active low. This means:
- asserting them requires setting the register value to 0
- de-asserting them requires setting the register value to 1
Set the register value accordingly for these two reset lines by setting
the inverted the register value compared to all other reset lines.
Fixes: 189621726b
("clk: meson: meson8b: register the built-in reset controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200417184127.1319871-3-martin.blumenstingl@googlemail.com
This commit is contained in:
parent
da1978ac3d
commit
0d3051c790
1 changed files with 56 additions and 23 deletions
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@ -3506,54 +3506,87 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
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static const struct meson8b_clk_reset_line {
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u32 reg;
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u8 bit_idx;
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bool active_low;
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} meson8b_clk_reset_bits[] = {
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[CLKC_RESET_L2_CACHE_SOFT_RESET] = {
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.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30
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.reg = HHI_SYS_CPU_CLK_CNTL0,
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.bit_idx = 30,
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.active_low = false,
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},
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[CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
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.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29
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.reg = HHI_SYS_CPU_CLK_CNTL0,
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.bit_idx = 29,
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.active_low = false,
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},
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[CLKC_RESET_SCU_SOFT_RESET] = {
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.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28
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.reg = HHI_SYS_CPU_CLK_CNTL0,
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.bit_idx = 28,
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.active_low = false,
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},
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[CLKC_RESET_CPU3_SOFT_RESET] = {
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.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27
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.reg = HHI_SYS_CPU_CLK_CNTL0,
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.bit_idx = 27,
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.active_low = false,
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},
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[CLKC_RESET_CPU2_SOFT_RESET] = {
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.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26
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.reg = HHI_SYS_CPU_CLK_CNTL0,
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.bit_idx = 26,
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.active_low = false,
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},
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[CLKC_RESET_CPU1_SOFT_RESET] = {
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.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25
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.reg = HHI_SYS_CPU_CLK_CNTL0,
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.bit_idx = 25,
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.active_low = false,
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},
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[CLKC_RESET_CPU0_SOFT_RESET] = {
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.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24
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.reg = HHI_SYS_CPU_CLK_CNTL0,
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.bit_idx = 24,
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.active_low = false,
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},
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[CLKC_RESET_A5_GLOBAL_RESET] = {
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.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18
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.reg = HHI_SYS_CPU_CLK_CNTL0,
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.bit_idx = 18,
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.active_low = false,
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},
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[CLKC_RESET_A5_AXI_SOFT_RESET] = {
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.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17
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.reg = HHI_SYS_CPU_CLK_CNTL0,
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.bit_idx = 17,
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.active_low = false,
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},
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[CLKC_RESET_A5_ABP_SOFT_RESET] = {
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.reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16
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.reg = HHI_SYS_CPU_CLK_CNTL0,
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.bit_idx = 16,
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.active_low = false,
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},
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[CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
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.reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30
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.reg = HHI_SYS_CPU_CLK_CNTL1,
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.bit_idx = 30,
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.active_low = false,
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},
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[CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
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.reg = HHI_VID_CLK_CNTL, .bit_idx = 15
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.reg = HHI_VID_CLK_CNTL,
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.bit_idx = 15,
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.active_low = false,
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},
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[CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
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.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7
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.reg = HHI_VID_DIVIDER_CNTL,
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.bit_idx = 7,
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.active_low = false,
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},
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[CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
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.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3
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.reg = HHI_VID_DIVIDER_CNTL,
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.bit_idx = 3,
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.active_low = false,
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},
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[CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
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.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1
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.reg = HHI_VID_DIVIDER_CNTL,
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.bit_idx = 1,
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.active_low = true,
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},
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[CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
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.reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0
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.reg = HHI_VID_DIVIDER_CNTL,
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.bit_idx = 0,
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.active_low = true,
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},
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};
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@ -3562,22 +3595,22 @@ static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
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{
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struct meson8b_clk_reset *meson8b_clk_reset =
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container_of(rcdev, struct meson8b_clk_reset, reset);
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unsigned long flags;
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const struct meson8b_clk_reset_line *reset;
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unsigned int value = 0;
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unsigned long flags;
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if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
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return -EINVAL;
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reset = &meson8b_clk_reset_bits[id];
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if (assert != reset->active_low)
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value = BIT(reset->bit_idx);
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spin_lock_irqsave(&meson_clk_lock, flags);
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if (assert)
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regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
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BIT(reset->bit_idx), BIT(reset->bit_idx));
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else
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regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
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BIT(reset->bit_idx), 0);
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BIT(reset->bit_idx), value);
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spin_unlock_irqrestore(&meson_clk_lock, flags);
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