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platform/x86: pmc_atom: Fix SLP_TYPx bitfield mask

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[ Upstream commit 0a90ed8d0c ]

On Intel hardware the SLP_TYPx bitfield occupies bits 10-12 as per ACPI
specification (see Table 4.13 "PM1 Control Registers Fixed Hardware
Feature Control Bits" for the details).

Fix the mask and other related definitions accordingly.

Fixes: 93e5eadd1f ("x86/platform: New Intel Atom SOC power management controller driver")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220801113734.36131-1-andriy.shevchenko@linux.intel.com
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Andy Shevchenko 2022-08-01 14:37:31 +03:00 committed by Greg Kroah-Hartman
parent b0d3a4f4c3
commit 0d5bed97ff
2 changed files with 5 additions and 3 deletions
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2
drivers/platform/x86/pmc_atom.c
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@ -232,7 +232,7 @@ static void pmc_power_off(void)
pm1_cnt_port = acpi_base_addr + PM1_CNT;
pm1_cnt_value = inl(pm1_cnt_port);
pm1_cnt_value &= SLEEP_TYPE_MASK;
pm1_cnt_value &= ~SLEEP_TYPE_MASK;
pm1_cnt_value |= SLEEP_TYPE_S5;
pm1_cnt_value |= SLEEP_ENABLE;

6
include/linux/platform_data/x86/pmc_atom.h
View file

@ -7,6 +7,8 @@
#ifndef PMC_ATOM_H
#define PMC_ATOM_H
#include <linux/bits.h>
/* ValleyView Power Control Unit PCI Device ID */
#define PCI_DEVICE_ID_VLV_PMC 0x0F1C
/* CherryTrail Power Control Unit PCI Device ID */
@ -139,9 +141,9 @@
#define ACPI_MMIO_REG_LEN 0x100
#define PM1_CNT 0x4
#define SLEEP_TYPE_MASK 0xFFFFECFF
#define SLEEP_TYPE_MASK GENMASK(12, 10)
#define SLEEP_TYPE_S5 0x1C00
#define SLEEP_ENABLE 0x2000
#define SLEEP_ENABLE BIT(13)
extern int pmc_atom_read(int offset, u32 *value);