From c17e9377aa81664d94b4f2102559fcf2a01ec8e7 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 18 Apr 2016 07:12:00 +0300 Subject: [PATCH 01/13] ARM: dts: lpc32xx: set default clock rate of HCLK PLL Probably most of NXP LPC32xx boards have 13MHz main oscillator and therefore for HCLK PLL and ARM core clock rate default hardware setting is 16 * 13MHz = 208MHz, however a user may vary HCLK PLL/ARM core rate from 156MHz to about 266MHz for 13MHz clock source. The change explicitly defines HCLK PLL output rate to default 208MHz to overwrite any settings done by a bootloader, if needed it can be redefined in a board DTS file. Acked-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index c58d8da9ea2a..d7b84cd209db 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -294,6 +294,9 @@ clk: clock-controller@0 { clocks = <&xtal_32k>, <&xtal>; clock-names = "xtal_32k", "xtal"; + + assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>; + assigned-clock-rates = <208000000>; }; }; From 73fdaa0f332fcf301327053cff7e523a85b0e7c7 Mon Sep 17 00:00:00 2001 From: Sylvain Lemieux Date: Wed, 20 Apr 2016 09:20:58 -0400 Subject: [PATCH 02/13] ARM: dts: lpc32xx: add clock properties to spi nodes The change adds clock properties to spi peripheral devices, clock ids are taken from dt-bindings/clock/lpc32xx-clock.h Signed-off-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index d7b84cd209db..1b2f351e4a08 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -173,6 +173,7 @@ ssp0: ssp@20084000 { spi1: spi@20088000 { compatible = "nxp,lpc3220-spi"; reg = <0x20088000 0x1000>; + clocks = <&clk LPC32XX_CLK_SPI1>; }; ssp1: ssp@2008c000 { @@ -186,6 +187,7 @@ ssp1: ssp@2008c000 { spi2: spi@20090000 { compatible = "nxp,lpc3220-spi"; reg = <0x20090000 0x1000>; + clocks = <&clk LPC32XX_CLK_SPI2>; }; i2s0: i2s@20094000 { From 9a96877c2b08865685bb80338db7254cf76af55f Mon Sep 17 00:00:00 2001 From: Sylvain Lemieux Date: Wed, 20 Apr 2016 09:20:59 -0400 Subject: [PATCH 03/13] ARM: dts: phy3250: enable ssp0 Preparatory change prior to disabling SSPx controllers by default in the shared LPC32xx DTSI file. Signed-off-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/phy3250.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index a00d7ce7802b..26e070fe9a58 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts @@ -146,6 +146,7 @@ ssp0: ssp@20084000 { #size-cells = <0>; num-cs = <1>; cs-gpios = <&gpio 3 5 0>; + status = "okay"; eeprom: at25@0 { pl022,interface = <0>; From 961212e3fd1ee29d31f3c362f0bc854868679f63 Mon Sep 17 00:00:00 2001 From: Sylvain Lemieux Date: Wed, 20 Apr 2016 09:21:00 -0400 Subject: [PATCH 04/13] ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by default The SSP0/SPI1 and SSP1/SPI2 shared pinout and should be disable by default. Board specific dts should enable them, as needed. Signed-off-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 1b2f351e4a08..73c474610efa 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -162,32 +162,44 @@ apb { compatible = "simple-bus"; ranges = <0x20000000 0x20000000 0x30000000>; + /* + * ssp0 and spi1 are shared pins; + * enable one in your board dts, as needed. + */ ssp0: ssp@20084000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x20084000 0x1000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SSP0>; clock-names = "apb_pclk"; + status = "disabled"; }; spi1: spi@20088000 { compatible = "nxp,lpc3220-spi"; reg = <0x20088000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI1>; + status = "disabled"; }; + /* + * ssp1 and spi2 are shared pins; + * enable one in your board dts, as needed. + */ ssp1: ssp@2008c000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x2008c000 0x1000>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SSP1>; clock-names = "apb_pclk"; + status = "disabled"; }; spi2: spi@20090000 { compatible = "nxp,lpc3220-spi"; reg = <0x20090000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI2>; + status = "disabled"; }; i2s0: i2s@20094000 { From d839e821efc06031c927cabbbc1e976bc71f5d4f Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 25 Apr 2016 04:00:23 +0300 Subject: [PATCH 05/13] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2 NXP LPC32xx has three interrupt controllers, namely root Main Interrupt Controller (MIC) and two supplementary Sub Interrupt Controllers (SIC1 and SIC2), four interrupt outputs from SIC1 and SIC2 are connected to MIC. Acked-by: Rob Herring Acked-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- .../interrupt-controller/nxp,lpc3220-mic.txt | 70 ++++++++++++------- 1 file changed, 46 insertions(+), 24 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt index 539adca19e8f..38211f344dc8 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt @@ -1,38 +1,60 @@ -* NXP LPC32xx Main Interrupt Controller - (MIC, including SIC1 and SIC2 secondary controllers) +* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers Required properties: -- compatible: Should be "nxp,lpc3220-mic" -- interrupt-controller: Identifies the node as an interrupt controller. -- interrupt-parent: Empty for the interrupt controller itself -- #interrupt-cells: The number of cells to define the interrupts. Should be 2. - The first cell is the IRQ number - The second cell is used to specify mode: - 1 = low-to-high edge triggered - 2 = high-to-low edge triggered - 4 = active high level-sensitive - 8 = active low level-sensitive - Default for internal sources should be set to 4 (active high). -- reg: Should contain MIC registers location and length +- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic". +- reg: should contain IC registers location and length. +- interrupt-controller: identifies the node as an interrupt controller. +- #interrupt-cells: the number of cells to define an interrupt, should be 2. + The first cell is the IRQ number, the second cell is used to specify + one of the supported IRQ types: + IRQ_TYPE_EDGE_RISING = low-to-high edge triggered, + IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered, + IRQ_TYPE_LEVEL_HIGH = active high level-sensitive, + IRQ_TYPE_LEVEL_LOW = active low level-sensitive. + Reset value is IRQ_TYPE_LEVEL_LOW. + +Optional properties: +- interrupt-parent: empty for MIC interrupt controller, link to parent + MIC interrupt controller for SIC1 and SIC2 +- interrupts: empty for MIC interrupt controller, cascaded MIC + hardware interrupts for SIC1 and SIC2 Examples: - /* - * MIC - */ + + /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */ mic: interrupt-controller@40008000 { compatible = "nxp,lpc3220-mic"; + reg = <0x40008000 0x4000>; interrupt-controller; - interrupt-parent; #interrupt-cells = <2>; - reg = <0x40008000 0xC000>; }; - /* - * ADC - */ + sic1: interrupt-controller@4000c000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x4000c000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&mic>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>, + <30 IRQ_TYPE_LEVEL_LOW>; + }; + + sic2: interrupt-controller@40010000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x40010000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&mic>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>, + <31 IRQ_TYPE_LEVEL_LOW>; + }; + + /* ADC */ adc@40048000 { compatible = "nxp,lpc3220-adc"; reg = <0x40048000 0x1000>; - interrupt-parent = <&mic>; - interrupts = <39 4>; + interrupt-parent = <&sic1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; }; From 9b8ad3fb81ae198ac669a61717d3a55af1f06bf2 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 26 Apr 2016 00:02:23 +0300 Subject: [PATCH 06/13] ARM: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC The change adds separate device nodes for SIC1 and SIC2 interrupt controllers and reparents all defined SIC1 and SIC2 interrupt producers to the correspondent interrupt controller, this is needed to perform switching to a new LPC32xx MIC/SIC interrupt controller driver. Acked-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/lpc32xx.dtsi | 60 ++++++++++++++++++++++++---------- 1 file changed, 42 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 73c474610efa..e295e1ec82a5 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -92,7 +92,8 @@ usb { ohci: ohci@0 { compatible = "nxp,ohci-nxp", "usb-ohci"; reg = <0x0 0x300>; - interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&sic1>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&usbclk LPC32XX_USB_CLK_HOST>; status = "disabled"; }; @@ -100,10 +101,11 @@ ohci: ohci@0 { usbd: usbd@0 { compatible = "nxp,lpc3220-udc"; reg = <0x0 0x300>; - interrupts = <61 IRQ_TYPE_LEVEL_HIGH>, - <62 IRQ_TYPE_LEVEL_HIGH>, - <60 IRQ_TYPE_LEVEL_HIGH>, - <58 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&sic1>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, + <30 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_LOW>; clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; status = "disabled"; }; @@ -111,7 +113,8 @@ usbd: usbd@0 { i2cusb: i2c@300 { compatible = "nxp,pnx-i2c"; reg = <0x300 0x100>; - interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&sic1>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&usbclk LPC32XX_USB_CLK_I2C>; #address-cells = <1>; #size-cells = <0>; @@ -263,7 +266,8 @@ uart6: serial@40098000 { i2c1: i2c@400A0000 { compatible = "nxp,pnx-i2c"; reg = <0x400A0000 0x100>; - interrupts = <51 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&sic1>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; #size-cells = <0>; pnx,timeout = <0x64>; @@ -273,7 +277,8 @@ i2c1: i2c@400A0000 { i2c2: i2c@400A8000 { compatible = "nxp,pnx-i2c"; reg = <0x400A8000 0x100>; - interrupts = <50 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&sic1>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; #size-cells = <0>; pnx,timeout = <0x64>; @@ -314,19 +319,35 @@ clk: clock-controller@0 { }; }; - /* - * MIC Interrupt controller includes: - * MIC @40008000 - * SIC1 @4000C000 - * SIC2 @40010000 - */ mic: interrupt-controller@40008000 { compatible = "nxp,lpc3220-mic"; + reg = <0x40008000 0x4000>; interrupt-controller; - reg = <0x40008000 0xC000>; #interrupt-cells = <2>; }; + sic1: interrupt-controller@4000c000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x4000c000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&mic>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>, + <30 IRQ_TYPE_LEVEL_LOW>; + }; + + sic2: interrupt-controller@40010000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x40010000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&mic>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>, + <31 IRQ_TYPE_LEVEL_LOW>; + }; + uart1: serial@40014000 { compatible = "nxp,lpc3220-hsuart"; reg = <0x40014000 0x1000>; @@ -351,7 +372,8 @@ uart7: serial@4001c000 { rtc: rtc@40024000 { compatible = "nxp,lpc3220-rtc"; reg = <0x40024000 0x1000>; - interrupts = <52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&sic1>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_RTC>; }; @@ -404,7 +426,8 @@ timer0: timer@40044000 { adc: adc@40048000 { compatible = "nxp,lpc3220-adc"; reg = <0x40048000 0x1000>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&sic1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_ADC>; status = "disabled"; }; @@ -412,7 +435,8 @@ adc: adc@40048000 { tsc: tsc@40048000 { compatible = "nxp,lpc3220-tsc"; reg = <0x40048000 0x1000>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&sic1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_ADC>; status = "disabled"; }; From 1a096afc7c27f059ebec0805bd1f52a0152e6cbf Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 27 Apr 2016 00:10:28 +0300 Subject: [PATCH 07/13] ARM: dts: lpc32xx: ea3250: avoid extension of device nodes by absolute path The change simplifies layout of EA3250 board description by referencing device nodes of LPC32xx controllers by label. No functional change intended. Acked-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/ea3250.dts | 226 +++++++++++++++++------------------ 1 file changed, 110 insertions(+), 116 deletions(-) diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts index a4a281fe82af..7cf815a51235 100644 --- a/arch/arm/boot/dts/ea3250.dts +++ b/arch/arm/boot/dts/ea3250.dts @@ -25,119 +25,6 @@ memory { reg = <0x80000000 0x4000000>; }; - ahb { - mac: ethernet@31060000 { - phy-mode = "rmii"; - use-iram; - }; - - /* 128MB Flash via SLC NAND controller */ - slc: flash@20020000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <1>; - - nxp,wdr-clks = <14>; - nxp,wwidth = <260000000>; - nxp,whold = <104000000>; - nxp,wsetup = <200000000>; - nxp,rdr-clks = <14>; - nxp,rwidth = <34666666>; - nxp,rhold = <104000000>; - nxp,rsetup = <200000000>; - nand-on-flash-bbt; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - - mtd0@00000000 { - label = "ea3250-boot"; - reg = <0x00000000 0x00080000>; - read-only; - }; - - mtd1@00080000 { - label = "ea3250-uboot"; - reg = <0x00080000 0x000c0000>; - read-only; - }; - - mtd2@00140000 { - label = "ea3250-kernel"; - reg = <0x00140000 0x00400000>; - }; - - mtd3@00540000 { - label = "ea3250-rootfs"; - reg = <0x00540000 0x07ac0000>; - }; - }; - - apb { - uart5: serial@40090000 { - status = "okay"; - }; - - uart3: serial@40080000 { - status = "okay"; - }; - - uart6: serial@40098000 { - status = "okay"; - }; - - i2c1: i2c@400A0000 { - clock-frequency = <100000>; - - eeprom@50 { - compatible = "at,24c256"; - reg = <0x50>; - }; - - eeprom@57 { - compatible = "at,24c64"; - reg = <0x57>; - }; - - uda1380: uda1380@18 { - compatible = "nxp,uda1380"; - reg = <0x18>; - power-gpio = <&gpio 0x59 0>; - reset-gpio = <&gpio 0x51 0>; - dac-clk = "wspll"; - }; - - pca9532: pca9532@60 { - compatible = "nxp,pca9532"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x60>; - }; - }; - - i2c2: i2c@400A8000 { - clock-frequency = <100000>; - }; - - sd@20098000 { - wp-gpios = <&pca9532 5 0>; - cd-gpios = <&pca9532 4 0>; - cd-inverted; - bus-width = <4>; - status = "okay"; - }; - }; - - fab { - uart1: serial@40014000 { - status = "okay"; - }; - - /* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ - adc@40048000 { - status = "okay"; - }; - }; - }; - gpio_keys { compatible = "gpio-keys"; #address-cells = <1>; @@ -258,12 +145,44 @@ lede8 { }; }; -/* Here, choose exactly one from: ohci, usbd */ -&ohci /* &usbd */ { - transceiver = <&isp1301>; +/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ +&adc { status = "okay"; }; +&i2c1 { + clock-frequency = <100000>; + + uda1380: uda1380@18 { + compatible = "nxp,uda1380"; + reg = <0x18>; + power-gpio = <&gpio 0x59 0>; + reset-gpio = <&gpio 0x51 0>; + dac-clk = "wspll"; + }; + + eeprom@50 { + compatible = "at,24c256"; + reg = <0x50>; + }; + + eeprom@57 { + compatible = "at,24c64"; + reg = <0x57>; + }; + + pca9532: pca9532@60 { + compatible = "nxp,pca9532"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x60>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + &i2cusb { clock-frequency = <100000>; @@ -272,3 +191,78 @@ isp1301: usb-transceiver@2d { reg = <0x2d>; }; }; + +&mac { + phy-mode = "rmii"; + use-iram; +}; + +/* Here, choose exactly one from: ohci, usbd */ +&ohci /* &usbd */ { + transceiver = <&isp1301>; + status = "okay"; +}; + +&sd { + wp-gpios = <&pca9532 5 0>; + cd-gpios = <&pca9532 4 0>; + cd-inverted; + bus-width = <4>; + status = "okay"; +}; + +/* 128MB Flash via SLC NAND controller */ +&slc { + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + nxp,wdr-clks = <14>; + nxp,wwidth = <260000000>; + nxp,whold = <104000000>; + nxp,wsetup = <200000000>; + nxp,rdr-clks = <14>; + nxp,rwidth = <34666666>; + nxp,rhold = <104000000>; + nxp,rsetup = <200000000>; + nand-on-flash-bbt; + gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ + + mtd0@00000000 { + label = "ea3250-boot"; + reg = <0x00000000 0x00080000>; + read-only; + }; + + mtd1@00080000 { + label = "ea3250-uboot"; + reg = <0x00080000 0x000c0000>; + read-only; + }; + + mtd2@00140000 { + label = "ea3250-kernel"; + reg = <0x00140000 0x00400000>; + }; + + mtd3@00540000 { + label = "ea3250-rootfs"; + reg = <0x00540000 0x07ac0000>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&uart6 { + status = "okay"; +}; From 72fa28e266317488738cded858c18c67488c2c04 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 27 Apr 2016 00:10:29 +0300 Subject: [PATCH 08/13] ARM: dts: lpc32xx: ea3250: add NAND partitions device node To declare MTD OF partitions NAND controller device node should have a special 'partitions' subnode, the change removes a debug message from mtd/ofpart on boot: nxp_lpc3220_slc: 'partitions' subnode not found on /ahb/flash@20020000. Trying to parse direct subnodes as partitions. Acked-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/ea3250.dts | 42 ++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts index 7cf815a51235..9637ac507302 100644 --- a/arch/arm/boot/dts/ea3250.dts +++ b/arch/arm/boot/dts/ea3250.dts @@ -213,8 +213,6 @@ &sd { /* 128MB Flash via SLC NAND controller */ &slc { - #address-cells = <1>; - #size-cells = <1>; status = "okay"; nxp,wdr-clks = <14>; @@ -228,26 +226,32 @@ &slc { nand-on-flash-bbt; gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - mtd0@00000000 { - label = "ea3250-boot"; - reg = <0x00000000 0x00080000>; - read-only; - }; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - mtd1@00080000 { - label = "ea3250-uboot"; - reg = <0x00080000 0x000c0000>; - read-only; - }; + mtd0@00000000 { + label = "ea3250-boot"; + reg = <0x00000000 0x00080000>; + read-only; + }; - mtd2@00140000 { - label = "ea3250-kernel"; - reg = <0x00140000 0x00400000>; - }; + mtd1@00080000 { + label = "ea3250-uboot"; + reg = <0x00080000 0x000c0000>; + read-only; + }; - mtd3@00540000 { - label = "ea3250-rootfs"; - reg = <0x00540000 0x07ac0000>; + mtd2@00140000 { + label = "ea3250-kernel"; + reg = <0x00140000 0x00400000>; + }; + + mtd3@00540000 { + label = "ea3250-rootfs"; + reg = <0x00540000 0x07ac0000>; + }; }; }; From 118e24cd626b8857b94eefec6f1108fef4017e51 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 27 Apr 2016 00:10:30 +0300 Subject: [PATCH 09/13] ARM: dts: lpc32xx: ea3250: fix Atmel at24 eeprom vendor There is no 'at' hardware vendor defined yet, correct vendor prefix for Atmel is 'atmel'. Acked-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/ea3250.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts index 9637ac507302..52b3ed10283a 100644 --- a/arch/arm/boot/dts/ea3250.dts +++ b/arch/arm/boot/dts/ea3250.dts @@ -162,12 +162,12 @@ uda1380: uda1380@18 { }; eeprom@50 { - compatible = "at,24c256"; + compatible = "atmel,24c256"; reg = <0x50>; }; eeprom@57 { - compatible = "at,24c64"; + compatible = "atmel,24c64"; reg = <0x57>; }; From d9a95d57647bc93f41f13a4ec6eafc1ebef7b533 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 27 Apr 2016 00:10:31 +0300 Subject: [PATCH 10/13] ARM: dts: lpc32xx: ea3250: add SoC name prefix to board dts file To simplify matching of DTS files of all NXP LPC32xx powered boards by a file name add 'lpc3250' prefix to Embedded Artists LPC3250 board dts file. Acked-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/Makefile | 3 ++- arch/arm/boot/dts/{ea3250.dts => lpc3250-ea3250.dts} | 0 2 files changed, 2 insertions(+), 1 deletion(-) rename arch/arm/boot/dts/{ea3250.dts => lpc3250-ea3250.dts} (100%) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 95c1923ce6fa..9f8b14fd5b26 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -241,7 +241,8 @@ dtb-$(CONFIG_ARCH_LPC18XX) += \ lpc4350-hitex-eval.dtb \ lpc4357-ea4357-devkit.dtb dtb-$(CONFIG_ARCH_LPC32XX) += \ - ea3250.dtb phy3250.dtb + lpc3250-ea3250.dtb \ + phy3250.dtb dtb-$(CONFIG_MACH_MESON6) += \ meson6-atv1200.dtb dtb-$(CONFIG_MACH_MESON8) += \ diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/lpc3250-ea3250.dts similarity index 100% rename from arch/arm/boot/dts/ea3250.dts rename to arch/arm/boot/dts/lpc3250-ea3250.dts From 6101f4bcb3d087b39a1d105d07bc72c9bd1194cb Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 27 Apr 2016 00:10:32 +0300 Subject: [PATCH 11/13] ARM: dts: lpc32xx: phy3250: avoid extension of device nodes by absolute path The change simplifies layout of PHY3250 board description by referencing device nodes of LPC32xx controllers by label. No functional change intended. Acked-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/phy3250.dts | 282 +++++++++++++++++----------------- 1 file changed, 138 insertions(+), 144 deletions(-) diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index 26e070fe9a58..c1a6e624bf19 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts @@ -56,147 +56,6 @@ sd_reg: regulator@2 { }; }; - ahb { - mac: ethernet@31060000 { - phy-mode = "rmii"; - use-iram; - }; - - clcd@31040000 { - status = "okay"; - }; - - /* 64MB Flash via SLC NAND controller */ - slc: flash@20020000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <1>; - - nxp,wdr-clks = <14>; - nxp,wwidth = <40000000>; - nxp,whold = <100000000>; - nxp,wsetup = <100000000>; - nxp,rdr-clks = <14>; - nxp,rwidth = <40000000>; - nxp,rhold = <66666666>; - nxp,rsetup = <100000000>; - nand-on-flash-bbt; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - - mtd0@00000000 { - label = "phy3250-boot"; - reg = <0x00000000 0x00064000>; - read-only; - }; - - mtd1@00064000 { - label = "phy3250-uboot"; - reg = <0x00064000 0x00190000>; - read-only; - }; - - mtd2@001f4000 { - label = "phy3250-ubt-prms"; - reg = <0x001f4000 0x00010000>; - }; - - mtd3@00204000 { - label = "phy3250-kernel"; - reg = <0x00204000 0x00400000>; - }; - - mtd4@00604000 { - label = "phy3250-rootfs"; - reg = <0x00604000 0x039fc000>; - }; - }; - - apb { - uart5: serial@40090000 { - status = "okay"; - }; - - uart3: serial@40080000 { - status = "okay"; - }; - - i2c1: i2c@400A0000 { - clock-frequency = <100000>; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - uda1380: uda1380@18 { - compatible = "nxp,uda1380"; - reg = <0x18>; - power-gpio = <&gpio 0x59 0>; - reset-gpio = <&gpio 0x51 0>; - dac-clk = "wspll"; - }; - }; - - i2c2: i2c@400A8000 { - clock-frequency = <100000>; - }; - - ssp0: ssp@20084000 { - #address-cells = <1>; - #size-cells = <0>; - num-cs = <1>; - cs-gpios = <&gpio 3 5 0>; - status = "okay"; - - eeprom: at25@0 { - pl022,interface = <0>; - pl022,com-mode = <0>; - pl022,rx-level-trig = <1>; - pl022,tx-level-trig = <1>; - pl022,ctrl-len = <11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - - at25,byte-len = <0x8000>; - at25,addr-mode = <2>; - at25,page-size = <64>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - }; - }; - - sd@20098000 { - wp-gpios = <&gpio 3 0 0>; - cd-gpios = <&gpio 3 1 0>; - cd-inverted; - bus-width = <4>; - vmmc-supply = <&sd_reg>; - status = "okay"; - }; - }; - - fab { - uart2: serial@40018000 { - status = "okay"; - }; - - tsc@40048000 { - status = "okay"; - }; - - key@40050000 { - status = "okay"; - keypad,num-rows = <1>; - keypad,num-columns = <1>; - nxp,debounce-delay-ms = <3>; - nxp,scan-delay-ms = <34>; - linux,keymap = <0x00000002>; - }; - }; - }; - leds { compatible = "gpio-leds"; @@ -212,12 +71,31 @@ led1 { /* green */ }; }; -/* Here, choose exactly one from: ohci, usbd */ -&ohci /* &usbd */ { - transceiver = <&isp1301>; +&clcd { status = "okay"; }; +&i2c1 { + clock-frequency = <100000>; + + uda1380: uda1380@18 { + compatible = "nxp,uda1380"; + reg = <0x18>; + power-gpio = <&gpio 0x59 0>; + reset-gpio = <&gpio 0x51 0>; + dac-clk = "wspll"; + }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + &i2cusb { clock-frequency = <100000>; @@ -226,3 +104,119 @@ isp1301: usb-transceiver@2c { reg = <0x2c>; }; }; + +&key { + keypad,num-rows = <1>; + keypad,num-columns = <1>; + nxp,debounce-delay-ms = <3>; + nxp,scan-delay-ms = <34>; + linux,keymap = <0x00000002>; + status = "okay"; +}; + +&mac { + phy-mode = "rmii"; + use-iram; +}; + +/* Here, choose exactly one from: ohci, usbd */ +&ohci /* &usbd */ { + transceiver = <&isp1301>; + status = "okay"; +}; + +&sd { + wp-gpios = <&gpio 3 0 0>; + cd-gpios = <&gpio 3 1 0>; + cd-inverted; + bus-width = <4>; + vmmc-supply = <&sd_reg>; + status = "okay"; +}; + +/* 64MB Flash via SLC NAND controller */ +&slc { + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + + nxp,wdr-clks = <14>; + nxp,wwidth = <40000000>; + nxp,whold = <100000000>; + nxp,wsetup = <100000000>; + nxp,rdr-clks = <14>; + nxp,rwidth = <40000000>; + nxp,rhold = <66666666>; + nxp,rsetup = <100000000>; + nand-on-flash-bbt; + gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ + + mtd0@00000000 { + label = "phy3250-boot"; + reg = <0x00000000 0x00064000>; + read-only; + }; + + mtd1@00064000 { + label = "phy3250-uboot"; + reg = <0x00064000 0x00190000>; + read-only; + }; + + mtd2@001f4000 { + label = "phy3250-ubt-prms"; + reg = <0x001f4000 0x00010000>; + }; + + mtd3@00204000 { + label = "phy3250-kernel"; + reg = <0x00204000 0x00400000>; + }; + + mtd4@00604000 { + label = "phy3250-rootfs"; + reg = <0x00604000 0x039fc000>; + }; +}; + +&ssp0 { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + cs-gpios = <&gpio 3 5 0>; + status = "okay"; + + eeprom: at25@0 { + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <5000000>; + + pl022,interface = <0>; + pl022,com-mode = <0>; + pl022,rx-level-trig = <1>; + pl022,tx-level-trig = <1>; + pl022,ctrl-len = <11>; + pl022,wait-state = <0>; + pl022,duplex = <0>; + + at25,byte-len = <0x8000>; + at25,addr-mode = <2>; + at25,page-size = <64>; + }; +}; + +&tsc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; From 9cfde0a1fede26cbeff0b6eba48bf7fd375e5c8c Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 27 Apr 2016 00:10:33 +0300 Subject: [PATCH 12/13] ARM: dts: lpc32xx: phy3250: add NAND partitions device node To declare MTD OF partitions NAND controller device node should have a special 'partitions' subnode, the change removes a debug message from mtd/ofpart on boot: nxp_lpc3220_slc: 'partitions' subnode not found on /ahb/flash@20020000. Trying to parse direct subnodes as partitions. Acked-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/phy3250.dts | 50 +++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 23 deletions(-) diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index c1a6e624bf19..fd95e2b10357 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts @@ -136,8 +136,6 @@ &sd { /* 64MB Flash via SLC NAND controller */ &slc { - #address-cells = <1>; - #size-cells = <1>; status = "okay"; nxp,wdr-clks = <14>; @@ -151,31 +149,37 @@ &slc { nand-on-flash-bbt; gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - mtd0@00000000 { - label = "phy3250-boot"; - reg = <0x00000000 0x00064000>; - read-only; - }; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - mtd1@00064000 { - label = "phy3250-uboot"; - reg = <0x00064000 0x00190000>; - read-only; - }; + mtd0@00000000 { + label = "phy3250-boot"; + reg = <0x00000000 0x00064000>; + read-only; + }; - mtd2@001f4000 { - label = "phy3250-ubt-prms"; - reg = <0x001f4000 0x00010000>; - }; + mtd1@00064000 { + label = "phy3250-uboot"; + reg = <0x00064000 0x00190000>; + read-only; + }; - mtd3@00204000 { - label = "phy3250-kernel"; - reg = <0x00204000 0x00400000>; - }; + mtd2@001f4000 { + label = "phy3250-ubt-prms"; + reg = <0x001f4000 0x00010000>; + }; - mtd4@00604000 { - label = "phy3250-rootfs"; - reg = <0x00604000 0x039fc000>; + mtd3@00204000 { + label = "phy3250-kernel"; + reg = <0x00204000 0x00400000>; + }; + + mtd4@00604000 { + label = "phy3250-rootfs"; + reg = <0x00604000 0x039fc000>; + }; }; }; From 3ff11fe8e8195d87090df9ffabfc85b4d35054c2 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 27 Apr 2016 00:10:34 +0300 Subject: [PATCH 13/13] ARM: dts: lpc32xx: phy3250: add SoC name prefix to board dts file To simplify matching of DTS files of all NXP LPC32xx powered boards by a file name add 'lpc3250' prefix to PHYTEC PHYCORE-LPC3250 board dts file. Acked-by: Sylvain Lemieux Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/Makefile | 2 +- arch/arm/boot/dts/{phy3250.dts => lpc3250-phy3250.dts} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/boot/dts/{phy3250.dts => lpc3250-phy3250.dts} (100%) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9f8b14fd5b26..4733ec9e5b23 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -242,7 +242,7 @@ dtb-$(CONFIG_ARCH_LPC18XX) += \ lpc4357-ea4357-devkit.dtb dtb-$(CONFIG_ARCH_LPC32XX) += \ lpc3250-ea3250.dtb \ - phy3250.dtb + lpc3250-phy3250.dtb dtb-$(CONFIG_MACH_MESON6) += \ meson6-atv1200.dtb dtb-$(CONFIG_MACH_MESON8) += \ diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts similarity index 100% rename from arch/arm/boot/dts/phy3250.dts rename to arch/arm/boot/dts/lpc3250-phy3250.dts