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drm/amd/display: Add new sequence for 4-lane HBR3 on vendor specific retimers
[Why] In some vendor specific retimer setups for downstream 4-lane HBR3 configuration, the sink will show severe corruption (horizontal shifting) and intermittent blanking. [How] Add new retimer programming sequence before clock recovery when 4 lanes are active. Reviewed-by: Michael Strauss <michael.strauss@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ad4455c614
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1 changed files with 66 additions and 1 deletions
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@ -236,6 +236,11 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence_legacy(
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uint32_t pre_disable_intercept_delay_ms = 0;
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uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0};
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uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0};
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const uint8_t vendor_lttpr_write_data_4lane_1[4] = {0x1, 0x6E, 0xF2, 0x19};
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const uint8_t vendor_lttpr_write_data_4lane_2[4] = {0x1, 0x6B, 0xF2, 0x01};
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const uint8_t vendor_lttpr_write_data_4lane_3[4] = {0x1, 0x6D, 0xF2, 0x18};
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const uint8_t vendor_lttpr_write_data_4lane_4[4] = {0x1, 0x6C, 0xF2, 0x03};
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const uint8_t vendor_lttpr_write_data_4lane_5[4] = {0x1, 0x03, 0xF3, 0x06};
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uint32_t vendor_lttpr_write_address = 0xF004F;
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enum link_training_result status = LINK_TRAINING_SUCCESS;
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uint8_t lane = 0;
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@ -338,6 +343,34 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence_legacy(
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DP_DOWNSPREAD_CTRL,
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lt_settings->link_settings.link_spread);
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if (lt_settings->link_settings.lane_count == LANE_COUNT_FOUR) {
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core_link_write_dpcd(
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link,
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vendor_lttpr_write_address,
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&vendor_lttpr_write_data_4lane_1[0],
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sizeof(vendor_lttpr_write_data_4lane_1));
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core_link_write_dpcd(
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link,
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vendor_lttpr_write_address,
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&vendor_lttpr_write_data_4lane_2[0],
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sizeof(vendor_lttpr_write_data_4lane_2));
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core_link_write_dpcd(
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link,
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vendor_lttpr_write_address,
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&vendor_lttpr_write_data_4lane_3[0],
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sizeof(vendor_lttpr_write_data_4lane_3));
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core_link_write_dpcd(
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link,
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vendor_lttpr_write_address,
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&vendor_lttpr_write_data_4lane_4[0],
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sizeof(vendor_lttpr_write_data_4lane_4));
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core_link_write_dpcd(
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link,
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vendor_lttpr_write_address,
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&vendor_lttpr_write_data_4lane_5[0],
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sizeof(vendor_lttpr_write_data_4lane_5));
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}
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/* 2. Perform link training */
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/* Perform Clock Recovery Sequence */
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@ -598,7 +631,11 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
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uint32_t pre_disable_intercept_delay_ms = 0;
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uint8_t vendor_lttpr_write_data_vs[4] = {0x1, 0x51, 0x63, 0x0};
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uint8_t vendor_lttpr_write_data_pe[4] = {0x1, 0x52, 0x63, 0x0};
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const uint8_t vendor_lttpr_write_data_4lane_1[4] = {0x1, 0x6E, 0xF2, 0x19};
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const uint8_t vendor_lttpr_write_data_4lane_2[4] = {0x1, 0x6B, 0xF2, 0x01};
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const uint8_t vendor_lttpr_write_data_4lane_3[4] = {0x1, 0x6D, 0xF2, 0x18};
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const uint8_t vendor_lttpr_write_data_4lane_4[4] = {0x1, 0x6C, 0xF2, 0x03};
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const uint8_t vendor_lttpr_write_data_4lane_5[4] = {0x1, 0x03, 0xF3, 0x06};
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uint32_t vendor_lttpr_write_address = 0xF004F;
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enum link_training_result status = LINK_TRAINING_SUCCESS;
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uint8_t lane = 0;
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@ -701,6 +738,34 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence(
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DP_DOWNSPREAD_CTRL,
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lt_settings->link_settings.link_spread);
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if (lt_settings->link_settings.lane_count == LANE_COUNT_FOUR) {
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core_link_write_dpcd(
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link,
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vendor_lttpr_write_address,
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&vendor_lttpr_write_data_4lane_1[0],
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sizeof(vendor_lttpr_write_data_4lane_1));
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core_link_write_dpcd(
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link,
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vendor_lttpr_write_address,
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&vendor_lttpr_write_data_4lane_2[0],
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sizeof(vendor_lttpr_write_data_4lane_2));
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core_link_write_dpcd(
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link,
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vendor_lttpr_write_address,
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&vendor_lttpr_write_data_4lane_3[0],
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sizeof(vendor_lttpr_write_data_4lane_3));
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core_link_write_dpcd(
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link,
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vendor_lttpr_write_address,
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&vendor_lttpr_write_data_4lane_4[0],
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sizeof(vendor_lttpr_write_data_4lane_4));
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core_link_write_dpcd(
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link,
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vendor_lttpr_write_address,
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&vendor_lttpr_write_data_4lane_5[0],
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sizeof(vendor_lttpr_write_data_4lane_5));
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}
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/* 2. Perform link training */
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/* Perform Clock Recovery Sequence */
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