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synced 2024-08-27 19:29:37 +00:00
sata_mv hardreset rework
Rework and simplify sata_mv's hardreset code to take advantage of libata improvements since it was first coded. Also, get rid of the now unnecessary prereset, postreset, and phy_reset functions. This patch also paves the way for subsequent pmp support patches, which will follow once this one passes muster. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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commit
0d8be5cbff
1 changed files with 22 additions and 138 deletions
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@ -478,10 +478,8 @@ static void mv_port_stop(struct ata_port *ap);
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static void mv_qc_prep(struct ata_queued_cmd *qc);
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static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
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static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
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static int mv_prereset(struct ata_link *link, unsigned long deadline);
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static int mv_hardreset(struct ata_link *link, unsigned int *class,
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unsigned long deadline);
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static void mv_postreset(struct ata_link *link, unsigned int *classes);
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static void mv_eh_freeze(struct ata_port *ap);
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static void mv_eh_thaw(struct ata_port *ap);
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static void mv6_dev_config(struct ata_device *dev);
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@ -545,9 +543,7 @@ static struct ata_port_operations mv5_ops = {
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.freeze = mv_eh_freeze,
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.thaw = mv_eh_thaw,
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.prereset = mv_prereset,
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.hardreset = mv_hardreset,
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.postreset = mv_postreset,
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.error_handler = ata_std_error_handler, /* avoid SFF EH */
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.post_internal_cmd = ATA_OP_NULL,
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@ -1904,7 +1900,6 @@ static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
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* (but doesn't say what the problem might be). So we first try
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* to disable the EDMA engine before doing the ATA_RST operation.
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*/
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mv_stop_edma_engine(port_mmio);
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mv_reset_channel(hpriv, mmio, port);
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ZERO(0x028); /* command */
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@ -2184,7 +2179,6 @@ static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
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* (but doesn't say what the problem might be). So we first try
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* to disable the EDMA engine before doing the ATA_RST operation.
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*/
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mv_stop_edma_engine(port_mmio);
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mv_reset_channel(hpriv, mmio, port);
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ZERO(0x028); /* command */
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@ -2261,6 +2255,7 @@ static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
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{
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void __iomem *port_mmio = mv_port_base(mmio, port_no);
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mv_stop_edma_engine(port_mmio);
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writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
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if (!IS_GEN_I(hpriv)) {
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@ -2282,116 +2277,6 @@ static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
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mdelay(1);
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}
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/**
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* mv_phy_reset - Perform eDMA reset followed by COMRESET
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* @ap: ATA channel to manipulate
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*
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* Part of this is taken from __sata_phy_reset and modified to
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* not sleep since this routine gets called from interrupt level.
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*
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* LOCKING:
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* Inherited from caller. This is coded to safe to call at
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* interrupt level, i.e. it does not sleep.
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*/
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static void mv_phy_reset(struct ata_port *ap, unsigned int *class,
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unsigned long deadline)
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{
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struct mv_port_priv *pp = ap->private_data;
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struct mv_host_priv *hpriv = ap->host->private_data;
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void __iomem *port_mmio = mv_ap_base(ap);
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int retry = 5;
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u32 sstatus;
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VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
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#ifdef DEBUG
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{
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u32 sstatus, serror, scontrol;
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mv_scr_read(ap, SCR_STATUS, &sstatus);
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mv_scr_read(ap, SCR_ERROR, &serror);
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mv_scr_read(ap, SCR_CONTROL, &scontrol);
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DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
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"SCtrl 0x%08x\n", sstatus, serror, scontrol);
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}
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#endif
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/* Issue COMRESET via SControl */
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comreset_retry:
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sata_scr_write_flush(&ap->link, SCR_CONTROL, 0x301);
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msleep(1);
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sata_scr_write_flush(&ap->link, SCR_CONTROL, 0x300);
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msleep(20);
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do {
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sata_scr_read(&ap->link, SCR_STATUS, &sstatus);
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if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0))
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break;
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msleep(1);
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} while (time_before(jiffies, deadline));
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/* work around errata */
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if (IS_GEN_II(hpriv) &&
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(sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
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(retry-- > 0))
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goto comreset_retry;
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#ifdef DEBUG
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{
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u32 sstatus, serror, scontrol;
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mv_scr_read(ap, SCR_STATUS, &sstatus);
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mv_scr_read(ap, SCR_ERROR, &serror);
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mv_scr_read(ap, SCR_CONTROL, &scontrol);
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DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
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"SCtrl 0x%08x\n", sstatus, serror, scontrol);
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}
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#endif
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if (ata_link_offline(&ap->link)) {
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*class = ATA_DEV_NONE;
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return;
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}
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/* even after SStatus reflects that device is ready,
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* it seems to take a while for link to be fully
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* established (and thus Status no longer 0x80/0x7F),
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* so we poll a bit for that, here.
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*/
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retry = 20;
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while (1) {
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u8 drv_stat = ata_sff_check_status(ap);
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if ((drv_stat != 0x80) && (drv_stat != 0x7f))
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break;
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msleep(500);
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if (retry-- <= 0)
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break;
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if (time_after(jiffies, deadline))
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break;
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}
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/* FIXME: if we passed the deadline, the following
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* code probably produces an invalid result
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*/
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/* finally, read device signature from TF registers */
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*class = ata_sff_dev_classify(ap->link.device, 1, NULL);
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writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
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WARN_ON(pp->pp_flags & MV_PP_FLAG_EDMA_EN);
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VPRINTK("EXIT\n");
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}
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static int mv_prereset(struct ata_link *link, unsigned long deadline)
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{
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mv_stop_edma(link->ap);
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return 0;
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}
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static int mv_hardreset(struct ata_link *link, unsigned int *class,
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unsigned long deadline)
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{
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@ -2399,34 +2284,33 @@ static int mv_hardreset(struct ata_link *link, unsigned int *class,
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struct mv_host_priv *hpriv = ap->host->private_data;
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struct mv_port_priv *pp = ap->private_data;
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void __iomem *mmio = hpriv->base;
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int rc, attempts = 0, extra = 0;
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u32 sstatus;
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bool online;
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mv_reset_channel(hpriv, mmio, ap->port_no);
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pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
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mv_phy_reset(ap, class, deadline);
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return 0;
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}
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/* Workaround for errata FEr SATA#10 (part 2) */
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do {
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const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
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static void mv_postreset(struct ata_link *link, unsigned int *classes)
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{
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struct ata_port *ap = link->ap;
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u32 serr;
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rc = sata_link_hardreset(link, timing, deadline + extra, &online, NULL);
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if (rc) {
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ata_link_printk(link, KERN_ERR,
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"COMRESET failed (errno=%d)\n", rc);
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return rc;
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}
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sata_scr_read(link, SCR_STATUS, &sstatus);
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if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
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/* Force 1.5gb/s link speed and try again */
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mv_setup_ifctl(mv_ap_base(ap), 0);
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if (time_after(jiffies + HZ, deadline))
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extra = HZ; /* only extend it once, max */
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}
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} while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
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/* print link status */
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sata_print_link_status(link);
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/* clear SError */
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sata_scr_read(link, SCR_ERROR, &serr);
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sata_scr_write_flush(link, SCR_ERROR, serr);
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/* bail out if no device is present */
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if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
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DPRINTK("EXIT, no device\n");
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return;
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}
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/* set up device control */
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iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
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return online ? -EAGAIN : rc;
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}
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static void mv_eh_freeze(struct ata_port *ap)
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