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drm/amdgpu: use same vce state definition in dpm and powerplay
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
cf0978819c
commit
0d8de7ca0b
11 changed files with 36 additions and 56 deletions
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@ -554,7 +554,7 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
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((u8 *)entry + sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record));
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}
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for (i = 0; i < states->numEntries; i++) {
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if (i >= AMDGPU_MAX_VCE_LEVELS)
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if (i >= AMD_MAX_VCE_LEVELS)
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break;
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vce_clk = (VCEClockInfo *)
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((u8 *)&array->entries[0] +
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@ -52,17 +52,6 @@ enum amdgpu_dpm_event_src {
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AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
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};
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#define AMDGPU_MAX_VCE_LEVELS 6
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enum amdgpu_vce_level {
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AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
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AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
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AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
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AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
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AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
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AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
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};
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struct amdgpu_ps {
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u32 caps; /* vbios flags */
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u32 class; /* vbios flags */
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@ -74,7 +63,7 @@ struct amdgpu_ps {
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u32 evclk;
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u32 ecclk;
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bool vce_active;
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enum amdgpu_vce_level vce_level;
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enum amd_vce_level vce_level;
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/* asic priv */
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void *ps_priv;
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};
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@ -257,17 +246,6 @@ enum amdgpu_dpm_forced_level {
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AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
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};
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struct amdgpu_vce_state {
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/* vce clocks */
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u32 evclk;
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u32 ecclk;
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/* gpu clocks */
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u32 sclk;
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u32 mclk;
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u8 clk_idx;
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u8 pstate;
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};
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struct amdgpu_dpm_funcs {
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int (*get_temperature)(struct amdgpu_device *adev);
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int (*pre_set_power_state)(struct amdgpu_device *adev);
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@ -409,8 +387,8 @@ struct amdgpu_dpm {
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/* default uvd power state */
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struct amdgpu_ps *uvd_ps;
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/* vce requirements */
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struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
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enum amdgpu_vce_level vce_level;
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struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
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enum amd_vce_level vce_level;
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enum amd_pm_state_type state;
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enum amd_pm_state_type user_state;
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u32 platform_caps;
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@ -1135,7 +1135,7 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
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mutex_lock(&adev->pm.mutex);
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adev->pm.dpm.vce_active = true;
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/* XXX select vce level based on ring/task */
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adev->pm.dpm.vce_level = AMDGPU_VCE_LEVEL_AC_ALL;
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adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
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mutex_unlock(&adev->pm.mutex);
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} else {
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mutex_lock(&adev->pm.mutex);
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@ -5689,7 +5689,7 @@ static int ci_parse_power_table(struct amdgpu_device *adev)
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adev->pm.dpm.num_ps = state_array->ucNumEntries;
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/* fill in the vce power states */
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for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
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for (i = 0; i < AMD_MAX_VCE_LEVELS; i++) {
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u32 sclk, mclk;
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clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
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clock_info = (union pplib_clock_info *)
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@ -2796,7 +2796,7 @@ static int kv_parse_power_table(struct amdgpu_device *adev)
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adev->pm.dpm.num_ps = state_array->ucNumEntries;
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/* fill in the vce power states */
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for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
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for (i = 0; i < AMD_MAX_VCE_LEVELS; i++) {
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u32 sclk;
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clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
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clock_info = (union pplib_clock_info *)
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@ -7320,7 +7320,7 @@ static int si_parse_power_table(struct amdgpu_device *adev)
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adev->pm.dpm.num_ps = state_array->ucNumEntries;
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/* fill in the vce power states */
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for (i = 0; i < AMDGPU_MAX_VCE_LEVELS; i++) {
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for (i = 0; i < AMD_MAX_VCE_LEVELS; i++) {
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u32 sclk, mclk;
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clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
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clock_info = (union pplib_clock_info *)
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@ -84,6 +84,29 @@ enum amd_powergating_state {
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AMD_PG_STATE_UNGATE,
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};
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struct amd_vce_state {
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/* vce clocks */
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u32 evclk;
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u32 ecclk;
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/* gpu clocks */
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u32 sclk;
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u32 mclk;
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u8 clk_idx;
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u8 pstate;
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};
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#define AMD_MAX_VCE_LEVELS 6
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enum amd_vce_level {
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AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
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AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
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AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
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AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
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AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
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AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
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};
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/* CG flags */
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#define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
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#define AMD_CG_SUPPORT_GFX_MGLS (1 << 1)
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@ -1211,7 +1211,7 @@ static int ppt_get_num_of_vce_state_table_entries_v1_0(struct pp_hwmgr *hwmgr)
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}
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static int ppt_get_vce_state_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t i,
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struct pp_vce_state *vce_state, void **clock_info, uint32_t *flag)
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struct amd_vce_state *vce_state, void **clock_info, uint32_t *flag)
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{
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const ATOM_Tonga_VCE_State_Record *vce_state_record;
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ATOM_Tonga_SCLK_Dependency_Record *sclk_dep_record;
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@ -1315,7 +1315,7 @@ int get_powerplay_table_entry_v1_0(struct pp_hwmgr *hwmgr,
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hwmgr->num_vce_state_tables = i = ppt_get_num_of_vce_state_table_entries_v1_0(hwmgr);
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if ((i != 0) && (i <= PP_MAX_VCE_LEVELS)) {
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if ((i != 0) && (i <= AMD_MAX_VCE_LEVELS)) {
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for (j = 0; j < i; j++)
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ppt_get_vce_state_table_entry_v1_0(hwmgr, j, &(hwmgr->vce_states[j]), NULL, &flags);
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}
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@ -1523,7 +1523,7 @@ static int get_number_of_vce_state_table_entries(
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static int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
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unsigned long i,
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struct pp_vce_state *vce_state,
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struct amd_vce_state *vce_state,
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void **clock_info,
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unsigned long *flag)
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{
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@ -367,7 +367,7 @@ struct pp_table_func {
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int (*pptable_get_vce_state_table_entry)(
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struct pp_hwmgr *hwmgr,
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unsigned long i,
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struct pp_vce_state *vce_state,
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struct amd_vce_state *vce_state,
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void **clock_info,
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unsigned long *flag);
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};
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@ -586,18 +586,6 @@ struct phm_microcode_version_info {
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uint32_t NB;
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};
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#define PP_MAX_VCE_LEVELS 6
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enum PP_VCE_LEVEL {
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PP_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
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PP_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
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PP_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
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PP_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
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PP_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
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PP_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
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};
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enum PP_TABLE_VERSION {
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PP_TABLE_V0 = 0,
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PP_TABLE_V1,
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@ -620,7 +608,7 @@ struct pp_hwmgr {
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void *hardcode_pp_table;
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bool need_pp_table_upload;
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struct pp_vce_state vce_states[PP_MAX_VCE_LEVELS];
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struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
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uint32_t num_vce_state_tables;
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enum amd_dpm_forced_level dpm_level;
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@ -156,15 +156,6 @@ struct pp_power_state {
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struct pp_hw_power_state hardware;
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};
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/*Structure to hold a VCE state entry*/
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struct pp_vce_state {
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uint32_t evclk;
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uint32_t ecclk;
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uint32_t sclk;
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uint32_t mclk;
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};
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enum PP_MMProfilingState {
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PP_MMProfilingState_NA = 0,
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PP_MMProfilingState_Started,
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