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SoCFPGA dts updates for v5.20, part 2

Browse source 
- Update EMAC AXI settings for Cyclone5
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Merge tag 'socfpga_updates_for_v5.20_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/late

SoCFPGA dts updates for v5.20, part 2
- Update EMAC AXI settings for Cyclone5

* tag 'socfpga_updates_for_v5.20_part2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: dts: add EMAC AXI settings for Cyclone5
  arm64: dts: altera: socfpga_stratix10: move clocks out of soc node
  arm64: dts: Add support for Stratix 10 Software Virtual Platform
  dt-bindings: altera: document Stratix 10 SWVP compatibles
  arm64: dts: altera: adjust whitespace around '='
  arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC
  dt-bindings: altera: Add Chameleon v3 board
  ARM: dts: socfpga: Add Google Chameleon v3 devicetree
  ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts
  ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts
  ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi

Link: https://lore.kernel.org/r/20220728223237.3184243-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-08-02 16:09:12 +02:00
commit 0d98fbcf72
13 changed files with 291 additions and 92 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
Documentation/devicetree/bindings/arm/altera.yaml
View file

@ -25,7 +25,14 @@ properties:
items:
- enum:
- altr,socfpga-arria10-socdk
- enclustra,mercury-aa1
- const: altr,socfpga-arria10
- const: altr,socfpga
- description: Mercury+ AA1 boards
items:
- enum:
- google,chameleon-v3
- const: enclustra,mercury-aa1
- const: altr,socfpga-arria10
- const: altr,socfpga
@ -47,6 +54,7 @@ properties:
items:
- enum:
- altr,socfpga-stratix10-socdk
- altr,socfpga-stratix10-swvp
- const: altr,socfpga-stratix10
- description: SoCFPGA VT

2
arch/arm/boot/dts/Makefile
View file

@ -1148,7 +1148,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_mercury_aa1.dtb \
socfpga_arria10_chameleonv3.dtb \
socfpga_arria10_socdk_nand.dtb \
socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \

8
arch/arm/boot/dts/socfpga.dtsi
View file

@ -561,6 +561,12 @@ fpgamgr0: fpgamgr@ff706000 {
interrupts = <0 175 4>;
};
socfpga_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <0xf>;
snps,rd_osr_lmt = <0xf>;
snps,blen = <0 0 0 0 16 0 0>;
};
gmac0: ethernet@ff700000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
altr,sysmgr-syscon = <&sysmgr 0x60 0>;
@ -576,6 +582,7 @@ gmac0: ethernet@ff700000 {
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <4096>;
snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};
@ -594,6 +601,7 @@ gmac1: ethernet@ff702000 {
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <4096>;
snps,axi-config = <&socfpga_axi_setup>;
status = "disabled";
};

10
arch/arm/boot/dts/socfpga_arria10.dtsi
View file

@ -736,6 +736,16 @@ emac0-tx-ecc@ff8c0c00 {
<37 IRQ_TYPE_LEVEL_HIGH>;
};
sdmmca-ecc@ff8c2c00 {
compatible = "altr,socfpga-sdmmc-ecc";
reg = <0xff8c2c00 0x400>;
altr,ecc-parent = <&mmc>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
<47 IRQ_TYPE_LEVEL_HIGH>,
<16 IRQ_TYPE_LEVEL_HIGH>,
<48 IRQ_TYPE_LEVEL_HIGH>;
};
dma-ecc@ff8c8000 {
compatible = "altr,socfpga-dma-ecc";
reg = <0xff8c8000 0x400>;

90
arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts Normal file
View file

@ -0,0 +1,90 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022 Google LLC
*/
/dts-v1/;
#include "socfpga_arria10_mercury_aa1.dtsi"
/ {
model = "Google Chameleon V3";
compatible = "google,chameleon-v3", "enclustra,mercury-aa1",
"altr,socfpga-arria10", "altr,socfpga";
aliases {
serial0 = &uart0;
i2c0 = &i2c0;
i2c1 = &i2c1;
};
};
&gmac0 {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&i2c0 {
status = "okay";
ssm2603: audio-codec@1a {
compatible = "adi,ssm2603";
reg = <0x1a>;
};
};
&i2c1 {
status = "okay";
u80: gpio@21 {
compatible = "nxp,pca9535";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"SOM_AUD_MUTE",
"DP1_OUT_CEC_EN",
"DP2_OUT_CEC_EN",
"DP1_SOM_PS8469_CAD",
"DPD_SOM_PS8469_CAD",
"DP_OUT_PWR_EN",
"STM32_RST_L",
"STM32_BOOT0",
"FPGA_PROT",
"STM32_FPGA_COMM0",
"TP119",
"TP120",
"TP121",
"TP122",
"TP123",
"TP124";
};
};
&mmc {
status = "okay";
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};

48
arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts → arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi
View file

@ -1,5 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/*
* Copyright 2022 Google LLC
*/
#include "socfpga_arria10.dtsi"
@ -11,8 +13,6 @@ / {
aliases {
ethernet0 = &gmac0;
serial1 = &uart1;
i2c0 = &i2c0;
i2c1 = &i2c1;
};
memory@0 {
@ -26,24 +26,11 @@ chosen {
};
};
&eccmgr {
sdmmca-ecc@ff8c2c00 {
compatible = "altr,socfpga-sdmmc-ecc";
reg = <0xff8c2c00 0x400>;
altr,ecc-parent = <&mmc>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
<47 IRQ_TYPE_LEVEL_HIGH>,
<16 IRQ_TYPE_LEVEL_HIGH>,
<48 IRQ_TYPE_LEVEL_HIGH>;
};
};
&gmac0 {
phy-mode = "rgmii";
phy-addr = <0xffffffff>; /* probe for phy addr */
max-frame-size = <3800>;
status = "okay";
phy-handle = <&phy3>;
@ -69,22 +56,13 @@ phy3: ethernet-phy@3 {
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&i2c1 {
status = "okay";
atsha204a: crypto@64 {
compatible = "atmel,atsha204a";
reg = <0x64>;
};
isl12022: isl12022@6f {
status = "okay";
compatible = "isil,isl12022";
reg = <0x6f>;
};
@ -92,7 +70,6 @@ isl12022: isl12022@6f {
/* Following mappings are taken from arria10 socdk dts */
&mmc {
status = "okay";
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
@ -101,12 +78,3 @@ &mmc {
&osc1 {
clock-frequency = <33330000>;
};
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};

3
arch/arm64/Kconfig.platforms
View file

@ -248,7 +248,8 @@ config ARCH_INTEL_SOCFPGA
bool "Intel's SoCFPGA ARMv8 Families"
help
This enables support for Intel's SoCFPGA ARMv8 families:
Stratix 10 (ex. Altera), Agilex and eASIC N5X.
Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform,
Agilex and eASIC N5X.
config ARCH_SYNQUACER
bool "Socionext SynQuacer SoC Family"

3
arch/arm64/boot/dts/altera/Makefile
View file

@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \
socfpga_stratix10_socdk_nand.dtb
socfpga_stratix10_socdk_nand.dtb \
socfpga_stratix10_swvp.dtb

58
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View file

@ -97,6 +97,34 @@ intc: interrupt-controller@fffc1000 {
<0x0 0xfffc6000 0x0 0x2000>;
};
clocks {
cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
cb_intosc_ls_clk: cb-intosc-ls-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
f2s_free_clk: f2s-free-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
osc1: osc1 {
#clock-cells = <0>;
compatible = "fixed-clock";
};
qspi_clk: qspi-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
@ -119,34 +147,6 @@ clkmgr: clock-controller@ffd10000 {
#clock-cells = <1>;
};
clocks {
cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
cb_intosc_ls_clk: cb-intosc-ls-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
f2s_free_clk: f2s-free-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
osc1: osc1 {
#clock-cells = <0>;
compatible = "fixed-clock";
};
qspi_clk: qspi-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
};
};
gmac0: ethernet@ff800000 {
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
reg = <0xff800000 0x2000>;
@ -594,7 +594,7 @@ emac0-tx-ecc@ff8c0400 {
};
qspi: spi@ff8d2000 {
compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xff8d2000 0x100>,

10
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
View file

@ -52,12 +52,6 @@ ref_033v: regulator-v-ref {
};
soc {
clocks {
osc1 {
clock-frequency = <25000000>;
};
};
eccmgr {
sdmmca-ecc@ff8c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc",
@ -113,6 +107,10 @@ &mmc {
bus-width = <4>;
};
&osc1 {
clock-frequency = <25000000>;
};
&uart0 {
status = "okay";
};

10
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
View file

@ -52,12 +52,6 @@ ref_033v: regulator-v-ref {
};
soc {
clocks {
osc1 {
clock-frequency = <25000000>;
};
};
eccmgr {
sdmmca-ecc@ff8c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc",
@ -126,6 +120,10 @@ partition@200000 {
};
};
&osc1 {
clock-frequency = <25000000>;
};
&uart0 {
status = "okay";
};

117
arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts Normal file
View file

@ -0,0 +1,117 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022, Intel Corporation
*/
#include "socfpga_stratix10.dtsi"
/ {
model = "SOCFPGA Stratix 10 SWVP";
compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
aliases {
serial0 = &uart0;
serial1 = &uart1;
timer0 = &timer0;
timer1 = &timer1;
timer2 = &timer2;
timer3 = &timer3;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &gmac2;
};
chosen {
stdout-path = "serial1:115200n8";
linux,initrd-start = <0x10000000>;
linux,initrd-end = <0x125c8324>;
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
&cpu0 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x0000fff8>;
};
&cpu1 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x0000fff8>;
};
&cpu2 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x0000fff8>;
};
&cpu3 {
enable-method = "spin-table";
cpu-release-addr = <0x0 0x0000fff8>;
};
&osc1 {
clock-frequency = <25000000>;
};
&gmac0 {
status = "okay";
phy-mode = "rgmii";
phy-addr = <0xffffffff>;
snps,max-mtu = <0x0>;
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
phy-addr = <0xffffffff>;
};
&gmac2 {
status = "okay";
phy-mode = "rgmii";
phy-addr = <0xffffffff>;
};
&mmc {
status = "okay";
altr,dw-mshc-ciu-div = <0x3>;
altr,dw-mshc-sdr-timing = <0x0 0x3>;
cap-sd-highspeed;
cap-mmc-highspeed;
broken-cd;
bus-width = <4>;
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usb0 {
clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
status = "okay";
};
&usb1 {
clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
status = "okay";
};
&rst {
altr,modrst-offset = <0x20>;
};
&sysmgr {
reg = <0xffd12000 0x1000>;
interrupts = <0x0 0x10 0x4>;
cpu1-start-addr = <0xffd06230>;
};

14
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
View file

@ -581,7 +581,7 @@ eccmgr {
sdramedac {
compatible = "altr,sdram-edac-s10";
altr,sdr-syscon = <&sdr>;
interrupts = <16 4>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
};
ocram-ecc@ff8cc000 {
@ -589,7 +589,7 @@ ocram-ecc@ff8cc000 {
"altr,socfpga-a10-ocram-ecc";
reg = <0xff8cc000 0x100>;
altr,ecc-parent = <&ocram>;
interrupts = <1 4>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
usb0-ecc@ff8c4000 {
@ -597,7 +597,7 @@ usb0-ecc@ff8c4000 {
"altr,socfpga-usb-ecc";
reg = <0xff8c4000 0x100>;
altr,ecc-parent = <&usb0>;
interrupts = <2 4>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-rx-ecc@ff8c0000 {
@ -605,7 +605,7 @@ emac0-rx-ecc@ff8c0000 {
"altr,socfpga-eth-mac-ecc";
reg = <0xff8c0000 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <4 4>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-tx-ecc@ff8c0400 {
@ -613,7 +613,7 @@ emac0-tx-ecc@ff8c0400 {
"altr,socfpga-eth-mac-ecc";
reg = <0xff8c0400 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <5 4>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
};
sdmmca-ecc@ff8c8c00 {
@ -621,8 +621,8 @@ sdmmca-ecc@ff8c8c00 {
"altr,socfpga-sdmmc-ecc";
reg = <0xff8c8c00 0x100>;
altr,ecc-parent = <&mmc>;
interrupts = <14 4>,
<15 4>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
<15 IRQ_TYPE_LEVEL_HIGH>;
};
};