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drm/i915: Extract GT ring management
Although the ring management is much smaller compared to the other GT power management functions, continue the theme of extracting it out of the huge intel_pm.c for maintenance. Based on a patch by Chris Wilson. Signed-off-by: Andi Shyti <andi.shyti@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191020184139.9145-1-chris@chris-wilson.co.uk
This commit is contained in:
Andi Shyti
Chris Wilson
parent
8814c6d01f
commit
0dc3c562aa
10 changed files with 297 additions and 120 deletions
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@ -87,6 +87,7 @@ gt-y += \
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gt/intel_gt_pm_irq.o \
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gt/intel_gt_requests.o \
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gt/intel_hangcheck.o \
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gt/intel_llc.o \
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gt/intel_lrc.o \
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gt/intel_rc6.o \
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gt/intel_renderstate.o \
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@ -17,6 +17,7 @@
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#include "i915_vma.h"
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#include "intel_engine_types.h"
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#include "intel_llc_types.h"
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#include "intel_reset_types.h"
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#include "intel_rc6_types.h"
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#include "intel_wakeref.h"
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@ -79,6 +80,7 @@ struct intel_gt {
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*/
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intel_wakeref_t awake;
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struct intel_llc llc;
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struct intel_rc6 rc6;
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struct blocking_notifier_head pm_notifications;
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161
drivers/gpu/drm/i915/gt/intel_llc.c
Normal file
161
drivers/gpu/drm/i915/gt/intel_llc.c
Normal file
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@ -0,0 +1,161 @@
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/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#include <linux/cpufreq.h>
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#include "i915_drv.h"
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#include "intel_gt.h"
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#include "intel_llc.h"
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#include "intel_sideband.h"
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struct ia_constants {
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unsigned int min_gpu_freq;
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unsigned int max_gpu_freq;
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unsigned int min_ring_freq;
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unsigned int max_ia_freq;
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};
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static struct intel_gt *llc_to_gt(struct intel_llc *llc)
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{
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return container_of(llc, struct intel_gt, llc);
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}
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static unsigned int cpu_max_MHz(void)
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{
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struct cpufreq_policy *policy;
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unsigned int max_khz;
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policy = cpufreq_cpu_get(0);
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if (policy) {
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max_khz = policy->cpuinfo.max_freq;
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cpufreq_cpu_put(policy);
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} else {
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/*
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* Default to measured freq if none found, PCU will ensure we
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* don't go over
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*/
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max_khz = tsc_khz;
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}
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return max_khz / 1000;
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}
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static bool get_ia_constants(struct intel_llc *llc,
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struct ia_constants *consts)
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{
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struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
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struct intel_rps *rps = &i915->gt_pm.rps;
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if (rps->max_freq <= rps->min_freq)
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return false;
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consts->max_ia_freq = cpu_max_MHz();
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consts->min_ring_freq =
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intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf;
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/* convert DDR frequency from units of 266.6MHz to bandwidth */
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consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);
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consts->min_gpu_freq = rps->min_freq;
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consts->max_gpu_freq = rps->max_freq;
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if (INTEL_GEN(i915) >= 9) {
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/* Convert GT frequency to 50 HZ units */
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consts->min_gpu_freq /= GEN9_FREQ_SCALER;
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consts->max_gpu_freq /= GEN9_FREQ_SCALER;
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}
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return true;
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}
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static void calc_ia_freq(struct intel_llc *llc,
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unsigned int gpu_freq,
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const struct ia_constants *consts,
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unsigned int *out_ia_freq,
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unsigned int *out_ring_freq)
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{
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struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
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const int diff = consts->max_gpu_freq - gpu_freq;
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unsigned int ia_freq = 0, ring_freq = 0;
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if (INTEL_GEN(i915) >= 9) {
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/*
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* ring_freq = 2 * GT. ring_freq is in 100MHz units
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* No floor required for ring frequency on SKL.
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*/
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ring_freq = gpu_freq;
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} else if (INTEL_GEN(i915) >= 8) {
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/* max(2 * GT, DDR). NB: GT is 50MHz units */
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ring_freq = max(consts->min_ring_freq, gpu_freq);
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} else if (IS_HASWELL(i915)) {
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ring_freq = mult_frac(gpu_freq, 5, 4);
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ring_freq = max(consts->min_ring_freq, ring_freq);
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/* leave ia_freq as the default, chosen by cpufreq */
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} else {
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const int min_freq = 15;
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const int scale = 180;
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/*
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* On older processors, there is no separate ring
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* clock domain, so in order to boost the bandwidth
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* of the ring, we need to upclock the CPU (ia_freq).
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*
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* For GPU frequencies less than 750MHz,
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* just use the lowest ring freq.
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*/
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if (gpu_freq < min_freq)
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ia_freq = 800;
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else
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ia_freq = consts->max_ia_freq - diff * scale / 2;
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ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
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}
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*out_ia_freq = ia_freq;
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*out_ring_freq = ring_freq;
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}
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static void gen6_update_ring_freq(struct intel_llc *llc)
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{
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struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
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struct ia_constants consts;
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unsigned int gpu_freq;
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if (!get_ia_constants(llc, &consts))
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return;
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/*
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* For each potential GPU frequency, load a ring frequency we'd like
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* to use for memory access. We do this by specifying the IA frequency
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* the PCU should use as a reference to determine the ring frequency.
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*/
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for (gpu_freq = consts.max_gpu_freq;
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gpu_freq >= consts.min_gpu_freq;
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gpu_freq--) {
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unsigned int ia_freq, ring_freq;
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calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
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sandybridge_pcode_write(i915,
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GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
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ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
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ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
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gpu_freq);
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}
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}
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void intel_llc_enable(struct intel_llc *llc)
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{
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if (HAS_LLC(llc_to_gt(llc)->i915))
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gen6_update_ring_freq(llc);
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}
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void intel_llc_disable(struct intel_llc *llc)
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{
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/* Currently there is no HW configuration to be done to disable. */
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}
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#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
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#include "selftest_llc.c"
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#endif
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15
drivers/gpu/drm/i915/gt/intel_llc.h
Normal file
15
drivers/gpu/drm/i915/gt/intel_llc.h
Normal file
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@ -0,0 +1,15 @@
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/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef INTEL_LLC_H
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#define INTEL_LLC_H
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struct intel_llc;
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void intel_llc_enable(struct intel_llc *llc);
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void intel_llc_disable(struct intel_llc *llc);
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#endif /* INTEL_LLC_H */
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13
drivers/gpu/drm/i915/gt/intel_llc_types.h
Normal file
13
drivers/gpu/drm/i915/gt/intel_llc_types.h
Normal file
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@ -0,0 +1,13 @@
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/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef INTEL_LLC_TYPES_H
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#define INTEL_LLC_TYPES_H
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struct intel_llc {
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};
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#endif /* INTEL_LLC_TYPES_H */
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@ -5,6 +5,8 @@
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* Copyright © 2019 Intel Corporation
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*/
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#include "selftest_llc.h"
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static int live_gt_resume(void *arg)
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{
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struct intel_gt *gt = arg;
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@ -32,6 +34,13 @@ static int live_gt_resume(void *arg)
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err = -EINVAL;
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break;
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}
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err = st_llc_verify(>->llc);
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if (err) {
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pr_err("llc state not restored upon resume!\n");
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intel_gt_set_wedged_on_init(gt);
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break;
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}
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} while (!__igt_timeout(end_time, NULL));
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return err;
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77
drivers/gpu/drm/i915/gt/selftest_llc.c
Normal file
77
drivers/gpu/drm/i915/gt/selftest_llc.c
Normal file
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@ -0,0 +1,77 @@
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/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#include "intel_pm.h" /* intel_gpu_freq() */
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#include "selftest_llc.h"
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static int gen6_verify_ring_freq(struct intel_llc *llc)
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{
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struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
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struct ia_constants consts;
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intel_wakeref_t wakeref;
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unsigned int gpu_freq;
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int err = 0;
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wakeref = intel_runtime_pm_get(llc_to_gt(llc)->uncore->rpm);
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if (!get_ia_constants(llc, &consts)) {
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err = -ENODEV;
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goto out_rpm;
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}
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for (gpu_freq = consts.min_gpu_freq;
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gpu_freq <= consts.max_gpu_freq;
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gpu_freq++) {
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unsigned int ia_freq, ring_freq, found;
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u32 val;
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calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
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val = gpu_freq;
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if (sandybridge_pcode_read(i915,
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GEN6_PCODE_READ_MIN_FREQ_TABLE,
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&val, NULL)) {
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pr_err("Failed to read freq table[%d], range [%d, %d]\n",
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gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq);
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err = -ENXIO;
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break;
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}
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found = (val >> 0) & 0xff;
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if (found != ia_freq) {
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pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected CPU freq, found %d, expected %d\n",
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gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
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intel_gpu_freq(i915, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
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found, ia_freq);
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err = -EINVAL;
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break;
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}
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found = (val >> 8) & 0xff;
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if (found != ring_freq) {
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pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected ring freq, found %d, expected %d\n",
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gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
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intel_gpu_freq(i915, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
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found, ring_freq);
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err = -EINVAL;
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break;
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}
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}
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out_rpm:
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intel_runtime_pm_put(llc_to_gt(llc)->uncore->rpm, wakeref);
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return err;
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}
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int st_llc_verify(struct intel_llc *llc)
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{
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int err = 0;
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if (HAS_LLC(llc_to_gt(llc)->i915))
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err = gen6_verify_ring_freq(llc);
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return err;
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}
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14
drivers/gpu/drm/i915/gt/selftest_llc.h
Normal file
14
drivers/gpu/drm/i915/gt/selftest_llc.h
Normal file
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@ -0,0 +1,14 @@
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/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef SELFTEST_LLC_H
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#define SELFTEST_LLC_H
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struct intel_llc;
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int st_llc_verify(struct intel_llc *llc);
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#endif /* SELFTEST_LLC_H */
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@ -605,13 +605,8 @@ struct intel_rps {
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struct intel_rps_ei ei;
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};
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struct intel_llc_pstate {
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bool enabled;
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};
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struct intel_gen6_power_mgmt {
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struct intel_rps rps;
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struct intel_llc_pstate llc_pstate;
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};
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/* defined intel_pm.c */
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@ -25,7 +25,6 @@
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*
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*/
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#include <linux/cpufreq.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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@ -38,6 +37,8 @@
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#include "display/intel_fbc.h"
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#include "display/intel_sprite.h"
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#include "gt/intel_llc.h"
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#include "i915_drv.h"
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#include "i915_irq.h"
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#include "i915_trace.h"
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@ -7030,93 +7031,6 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
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intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
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}
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static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
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{
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struct intel_rps *rps = &dev_priv->gt_pm.rps;
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const int min_freq = 15;
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const int scaling_factor = 180;
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unsigned int gpu_freq;
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unsigned int max_ia_freq, min_ring_freq;
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unsigned int max_gpu_freq, min_gpu_freq;
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struct cpufreq_policy *policy;
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lockdep_assert_held(&rps->lock);
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if (rps->max_freq <= rps->min_freq)
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return;
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policy = cpufreq_cpu_get(0);
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if (policy) {
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max_ia_freq = policy->cpuinfo.max_freq;
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cpufreq_cpu_put(policy);
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} else {
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/*
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* Default to measured freq if none found, PCU will ensure we
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* don't go over
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*/
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max_ia_freq = tsc_khz;
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}
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/* Convert from kHz to MHz */
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max_ia_freq /= 1000;
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min_ring_freq = I915_READ(DCLK) & 0xf;
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/* convert DDR frequency from units of 266.6MHz to bandwidth */
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min_ring_freq = mult_frac(min_ring_freq, 8, 3);
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min_gpu_freq = rps->min_freq;
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max_gpu_freq = rps->max_freq;
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if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
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/* Convert GT frequency to 50 HZ units */
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min_gpu_freq /= GEN9_FREQ_SCALER;
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max_gpu_freq /= GEN9_FREQ_SCALER;
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}
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/*
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* For each potential GPU frequency, load a ring frequency we'd like
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* to use for memory access. We do this by specifying the IA frequency
|
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* the PCU should use as a reference to determine the ring frequency.
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*/
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for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
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const int diff = max_gpu_freq - gpu_freq;
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unsigned int ia_freq = 0, ring_freq = 0;
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if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
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/*
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* ring_freq = 2 * GT. ring_freq is in 100MHz units
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* No floor required for ring frequency on SKL.
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*/
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ring_freq = gpu_freq;
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} else if (INTEL_GEN(dev_priv) >= 8) {
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/* max(2 * GT, DDR). NB: GT is 50MHz units */
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ring_freq = max(min_ring_freq, gpu_freq);
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} else if (IS_HASWELL(dev_priv)) {
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ring_freq = mult_frac(gpu_freq, 5, 4);
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ring_freq = max(min_ring_freq, ring_freq);
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/* leave ia_freq as the default, chosen by cpufreq */
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} else {
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/* On older processors, there is no separate ring
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* clock domain, so in order to boost the bandwidth
|
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* of the ring, we need to upclock the CPU (ia_freq).
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*
|
||||
* For GPU frequencies less than 750MHz,
|
||||
* just use the lowest ring freq.
|
||||
*/
|
||||
if (gpu_freq < min_freq)
|
||||
ia_freq = 800;
|
||||
else
|
||||
ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
|
||||
ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
|
||||
}
|
||||
|
||||
sandybridge_pcode_write(dev_priv,
|
||||
GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
|
||||
ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
|
||||
ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
|
||||
gpu_freq);
|
||||
}
|
||||
}
|
||||
|
||||
static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
u32 val, rp0;
|
||||
|
|
@ -7965,18 +7879,6 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
|
|||
gen6_reset_rps_interrupts(dev_priv);
|
||||
}
|
||||
|
||||
static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
|
||||
{
|
||||
lockdep_assert_held(&i915->gt_pm.rps.lock);
|
||||
|
||||
if (!i915->gt_pm.llc_pstate.enabled)
|
||||
return;
|
||||
|
||||
/* Currently there is no HW configuration to be done to disable. */
|
||||
|
||||
i915->gt_pm.llc_pstate.enabled = false;
|
||||
}
|
||||
|
||||
static void intel_disable_rps(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
|
||||
|
|
@ -8004,23 +7906,11 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
|
|||
|
||||
intel_disable_rps(dev_priv);
|
||||
if (HAS_LLC(dev_priv))
|
||||
intel_disable_llc_pstate(dev_priv);
|
||||
intel_llc_disable(&dev_priv->gt.llc);
|
||||
|
||||
mutex_unlock(&dev_priv->gt_pm.rps.lock);
|
||||
}
|
||||
|
||||
static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
|
||||
{
|
||||
lockdep_assert_held(&i915->gt_pm.rps.lock);
|
||||
|
||||
if (i915->gt_pm.llc_pstate.enabled)
|
||||
return;
|
||||
|
||||
gen6_update_ring_freq(i915);
|
||||
|
||||
i915->gt_pm.llc_pstate.enabled = true;
|
||||
}
|
||||
|
||||
static void intel_enable_rps(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_rps *rps = &dev_priv->gt_pm.rps;
|
||||
|
|
@ -8064,8 +7954,8 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
|
|||
|
||||
if (HAS_RPS(dev_priv))
|
||||
intel_enable_rps(dev_priv);
|
||||
if (HAS_LLC(dev_priv))
|
||||
intel_enable_llc_pstate(dev_priv);
|
||||
|
||||
intel_llc_enable(&dev_priv->gt.llc);
|
||||
|
||||
mutex_unlock(&dev_priv->gt_pm.rps.lock);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue