From 0de0fe950f1b0f7b5eaa2ee4e93851eb905b1b77 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 4 Jul 2022 12:13:19 +0200 Subject: [PATCH] arm64: dts: mediatek: cherry: Enable MT6360 sub-pmic on I2C7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All devices of the Cherry platform have a MT6360 sub-pmic, providing two LDOs. Add the required node to enable the PMIC but without regulators yet, as these will be added in a later commit. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220704101321.44835-10-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index f68d8ff05b4d..c07d3ac79f62 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -161,6 +161,18 @@ &i2c7 { clock-frequency = <400000>; pinctrl-names = "default"; pinctrl-0 = <&i2c7_pins>; + + pmic@34 { + #interrupt-cells = <1>; + compatible = "mediatek,mt6360"; + reg = <0x34>; + interrupt-controller; + interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "IRQB"; + pinctrl-names = "default"; + pinctrl-0 = <&subpmic_default>; + wakeup-source; + }; }; &mmc0 { @@ -558,6 +570,14 @@ pins-miso { bias-pull-down; }; }; + + subpmic_default: subpmic-default-pins { + subpmic_pin_irq: pins-subpmic-int-n { + pinmux = ; + input-enable; + bias-pull-up; + }; + }; }; &pmic {