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ARM/arm64: KVM: correct PTE uncachedness check
Commite6fab54423
("ARM/arm64: KVM: test properly for a PTE's uncachedness") modified the logic to test whether a HYP or stage-2 mapping needs flushing, from [incorrectly] interpreting the page table attributes to [incorrectly] checking whether the PFN that backs the mapping is covered by host system RAM. The PFN number is part of the output of the translation, not the input, so we have to use pte_pfn() on the contents of the PTE, not __phys_to_pfn() on the HYP virtual address or stage-2 intermediate physical address. Fixes:e6fab54423
("ARM/arm64: KVM: test properly for a PTE's uncachedness") Cc: stable@vger.kernel.org Tested-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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parent
f6be563abb
commit
0de58f8528
1 changed files with 2 additions and 2 deletions
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@ -218,7 +218,7 @@ static void unmap_ptes(struct kvm *kvm, pmd_t *pmd,
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kvm_tlb_flush_vmid_ipa(kvm, addr);
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kvm_tlb_flush_vmid_ipa(kvm, addr);
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/* No need to invalidate the cache for device mappings */
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/* No need to invalidate the cache for device mappings */
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if (!kvm_is_device_pfn(__phys_to_pfn(addr)))
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if (!kvm_is_device_pfn(pte_pfn(old_pte)))
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kvm_flush_dcache_pte(old_pte);
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kvm_flush_dcache_pte(old_pte);
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put_page(virt_to_page(pte));
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put_page(virt_to_page(pte));
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@ -310,7 +310,7 @@ static void stage2_flush_ptes(struct kvm *kvm, pmd_t *pmd,
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pte = pte_offset_kernel(pmd, addr);
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pte = pte_offset_kernel(pmd, addr);
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do {
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do {
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if (!pte_none(*pte) && !kvm_is_device_pfn(__phys_to_pfn(addr)))
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if (!pte_none(*pte) && !kvm_is_device_pfn(pte_pfn(*pte)))
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kvm_flush_dcache_pte(*pte);
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kvm_flush_dcache_pte(*pte);
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} while (pte++, addr += PAGE_SIZE, addr != end);
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} while (pte++, addr += PAGE_SIZE, addr != end);
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}
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}
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