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drm/msm/mdp5: Don't get source of MDP core clock
The driver expects DT to provide the parent to MDP core clock. The only operation done to the parent clock is to set a rate. This can be achieved by setting the rate on the core clock itsef. Don't try to get the parent clock anymore. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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cbe4295a4c
commit
0e0d9dfeea
2 changed files with 2 additions and 6 deletions
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@ -627,9 +627,6 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
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if (ret)
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goto fail;
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ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk", true);
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if (ret)
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goto fail;
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ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src", true);
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if (ret)
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goto fail;
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ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk", true);
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@ -646,7 +643,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
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* rate first, then figure out hw revision, and then set a
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* more optimal rate:
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*/
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clk_set_rate(mdp5_kms->src_clk, 200000000);
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clk_set_rate(mdp5_kms->core_clk, 200000000);
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read_hw_revision(mdp5_kms, &major, &minor);
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@ -661,7 +658,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
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mdp5_kms->caps = config->hw->mdp.caps;
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/* TODO: compute core clock rate at runtime */
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clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk);
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clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk);
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/*
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* Some chipsets have a Shared Memory Pool (SMP), while others
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@ -49,7 +49,6 @@ struct mdp5_kms {
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struct clk *axi_clk;
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struct clk *ahb_clk;
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struct clk *src_clk;
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struct clk *core_clk;
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struct clk *lut_clk;
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struct clk *vsync_clk;
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