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[Blackfin] arch: relocate MAX_SWITCH_{D,I}_CPLBS from the header to the file where it actually gets used.
relocate MAX_SWITCH_{D,I}_CPLBS from the header to the file where it actually gets used. this way when we change CONFIG_MEM_SIZE in our kconfig, we only rebuild one or two files rather than a whole bunch that implicitly include cplb.h. this will also remove the ability to clear the swapcount on the fly, but i really dont think that functionality is important. ultimate goal is for CONFIG_MEM_SIZE to go away and calculate this value on the fly based on what u-boot programmed for us. Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
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parent
53eabf046b
commit
0e184c6b4f
3 changed files with 23 additions and 37 deletions
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@ -174,16 +174,6 @@ static int cplbinfo_read_proc(char *page, char **start, off_t off,
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return len;
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}
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static int cplbinfo_write_proc(struct file *file, const char __user *buffer,
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unsigned long count, void *data)
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{
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printk(KERN_INFO "Reset the CPLB swap in/out counts.\n");
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memset(ipdt_swapcount_table, 0, MAX_SWITCH_I_CPLBS * sizeof(unsigned long));
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memset(dpdt_swapcount_table, 0, MAX_SWITCH_D_CPLBS * sizeof(unsigned long));
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return count;
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}
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static int __init cplbinfo_init(void)
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{
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struct proc_dir_entry *entry;
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@ -193,7 +183,6 @@ static int __init cplbinfo_init(void)
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return -ENOMEM;
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entry->read_proc = cplbinfo_read_proc;
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entry->write_proc = cplbinfo_write_proc;
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entry->data = NULL;
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return 0;
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@ -26,6 +26,29 @@
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#include <asm/cplb.h>
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#include <asm/cplbinit.h>
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/*
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* Number of required data CPLB switchtable entries
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* MEMSIZE / 4 (we mostly install 4M page size CPLBs
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* approx 16 for smaller 1MB page size CPLBs for allignment purposes
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* 1 for L1 Data Memory
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* possibly 1 for L2 Data Memory
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* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
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* 1 for ASYNC Memory
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*/
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#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \
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+ ASYNC_MEMORY_CPLB_COVERAGE) * 2)
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/*
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* Number of required instruction CPLB switchtable entries
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* MEMSIZE / 4 (we mostly install 4M page size CPLBs
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* approx 12 for smaller 1MB page size CPLBs for allignment purposes
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* 1 for L1 Instruction Memory
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* possibly 1 for L2 Instruction Memory
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* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
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*/
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#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
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u_long icplb_table[MAX_CPLBS + 1];
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u_long dcplb_table[MAX_CPLBS + 1];
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@ -74,32 +74,6 @@
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#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
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ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
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/*
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* Number of required data CPLB switchtable entries
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* MEMSIZE / 4 (we mostly install 4M page size CPLBs
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* approx 16 for smaller 1MB page size CPLBs for allignment purposes
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* 1 for L1 Data Memory
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* possibly 1 for L2 Data Memory
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* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
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* 1 for ASYNC Memory
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*/
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#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \
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+ ASYNC_MEMORY_CPLB_COVERAGE) * 2)
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/*
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* Number of required instruction CPLB switchtable entries
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* MEMSIZE / 4 (we mostly install 4M page size CPLBs
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* approx 12 for smaller 1MB page size CPLBs for allignment purposes
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* 1 for L1 Instruction Memory
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* possibly 1 for L2 Instruction Memory
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* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
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*/
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#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
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#define CPLB_ENABLE_ICACHE_P 0
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#define CPLB_ENABLE_DCACHE_P 1
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#define CPLB_ENABLE_DCACHE2_P 2
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