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drm/amdgpu: drop client_id from VM
Use the fence context from the scheduler entity. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
c4f46f22c4
commit
0e36b9b2f9
3 changed files with 4 additions and 10 deletions
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@ -115,7 +115,7 @@ static int amdgpu_vmid_grab_reserved_locked(struct amdgpu_vm *vm,
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flushed = id->flushed_updates;
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flushed = id->flushed_updates;
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if ((amdgpu_vmid_had_gpu_reset(adev, id)) ||
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if ((amdgpu_vmid_had_gpu_reset(adev, id)) ||
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(atomic64_read(&id->owner) != vm->client_id) ||
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(atomic64_read(&id->owner) != vm->entity.fence_context) ||
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(job->vm_pd_addr != id->pd_gpu_addr) ||
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(job->vm_pd_addr != id->pd_gpu_addr) ||
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(updates && (!flushed || updates->context != flushed->context ||
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(updates && (!flushed || updates->context != flushed->context ||
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dma_fence_is_later(updates, flushed))) ||
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dma_fence_is_later(updates, flushed))) ||
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@ -144,7 +144,7 @@ static int amdgpu_vmid_grab_reserved_locked(struct amdgpu_vm *vm,
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id->flushed_updates = dma_fence_get(updates);
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id->flushed_updates = dma_fence_get(updates);
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}
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}
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id->pd_gpu_addr = job->vm_pd_addr;
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id->pd_gpu_addr = job->vm_pd_addr;
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atomic64_set(&id->owner, vm->client_id);
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atomic64_set(&id->owner, vm->entity.fence_context);
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job->vm_needs_flush = needs_flush;
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job->vm_needs_flush = needs_flush;
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if (needs_flush) {
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if (needs_flush) {
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dma_fence_put(id->last_flush);
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dma_fence_put(id->last_flush);
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@ -242,7 +242,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
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if (amdgpu_vmid_had_gpu_reset(adev, id))
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if (amdgpu_vmid_had_gpu_reset(adev, id))
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continue;
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continue;
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if (atomic64_read(&id->owner) != vm->client_id)
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if (atomic64_read(&id->owner) != vm->entity.fence_context)
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continue;
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continue;
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if (job->vm_pd_addr != id->pd_gpu_addr)
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if (job->vm_pd_addr != id->pd_gpu_addr)
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@ -291,7 +291,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
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id->pd_gpu_addr = job->vm_pd_addr;
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id->pd_gpu_addr = job->vm_pd_addr;
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dma_fence_put(id->flushed_updates);
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dma_fence_put(id->flushed_updates);
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id->flushed_updates = dma_fence_get(updates);
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id->flushed_updates = dma_fence_get(updates);
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atomic64_set(&id->owner, vm->client_id);
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atomic64_set(&id->owner, vm->entity.fence_context);
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needs_flush:
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needs_flush:
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job->vm_needs_flush = true;
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job->vm_needs_flush = true;
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@ -2256,7 +2256,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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uint64_t init_pde_value = 0;
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uint64_t init_pde_value = 0;
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vm->va = RB_ROOT_CACHED;
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vm->va = RB_ROOT_CACHED;
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vm->client_id = atomic64_inc_return(&adev->vm_manager.client_counter);
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for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
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for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
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vm->reserved_vmid[i] = NULL;
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vm->reserved_vmid[i] = NULL;
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spin_lock_init(&vm->status_lock);
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spin_lock_init(&vm->status_lock);
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@ -2502,7 +2501,6 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
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adev->vm_manager.seqno[i] = 0;
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adev->vm_manager.seqno[i] = 0;
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atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
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atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
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atomic64_set(&adev->vm_manager.client_counter, 0);
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spin_lock_init(&adev->vm_manager.prt_lock);
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spin_lock_init(&adev->vm_manager.prt_lock);
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atomic_set(&adev->vm_manager.num_prt_users, 0);
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atomic_set(&adev->vm_manager.num_prt_users, 0);
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@ -191,8 +191,6 @@ struct amdgpu_vm {
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/* Scheduler entity for page table updates */
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/* Scheduler entity for page table updates */
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struct drm_sched_entity entity;
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struct drm_sched_entity entity;
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/* client id and PASID (TODO: replace client_id with PASID) */
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u64 client_id;
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unsigned int pasid;
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unsigned int pasid;
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/* dedicated to vm */
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/* dedicated to vm */
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struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS];
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struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS];
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@ -230,8 +228,6 @@ struct amdgpu_vm_manager {
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struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
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struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
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unsigned vm_pte_num_rings;
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unsigned vm_pte_num_rings;
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atomic_t vm_pte_next_ring;
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atomic_t vm_pte_next_ring;
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/* client id counter */
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atomic64_t client_counter;
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/* partial resident texture handling */
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/* partial resident texture handling */
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spinlock_t prt_lock;
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spinlock_t prt_lock;
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