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clk: tegra: Use XUSB-compatible SATA PLL sequence
Use a sequence for enabling hardware control of the SATA PLL that works both when using the SATA lane with SATA and when using it with XUSB. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
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1 changed files with 11 additions and 0 deletions
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@ -112,6 +112,9 @@
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#define SATA_PLL_CFG0 0x490
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#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
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#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
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#define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
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#define SATA_PLL_CFG0_SEQ_START_STATE BIT(25)
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#define PLLE_MISC_PLLE_PTS BIT(8)
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#define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
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@ -1367,6 +1370,14 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
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/* Enable hw control of SATA pll */
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val = pll_readl(SATA_PLL_CFG0, pll);
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val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
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val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
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val |= SATA_PLL_CFG0_SEQ_START_STATE;
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pll_writel(val, SATA_PLL_CFG0, pll);
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udelay(1);
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val = pll_readl(SATA_PLL_CFG0, pll);
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val |= SATA_PLL_CFG0_SEQ_ENABLE;
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pll_writel(val, SATA_PLL_CFG0, pll);
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out:
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