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sky2: Added support for Optima EEE
This patch adds support for the Optima EEE chipset. Signed-off-by: Mirko Lindner <mlindner@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
03fc4721cd
commit
0e767324f2
2 changed files with 18 additions and 1 deletions
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@ -141,6 +141,7 @@ static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */
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{ 0 }
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{ 0 }
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};
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};
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@ -3349,6 +3350,17 @@ static void sky2_reset(struct sky2_hw *hw)
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sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
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sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
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reg);
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reg);
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if (hw->chip_id == CHIP_ID_YUKON_PRM &&
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hw->chip_rev == CHIP_REV_YU_PRM_A0) {
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/* change PHY Interrupt polarity to low active */
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reg = sky2_read16(hw, GPHY_CTRL);
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sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL);
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/* adapt HW for low active PHY Interrupt */
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reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL);
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sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1);
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}
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
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/* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
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/* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
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@ -4871,7 +4883,7 @@ static const char *sky2_name(u8 chipid, char *buf, int sz)
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"UL 2", /* 0xba */
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"UL 2", /* 0xba */
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"Unknown", /* 0xbb */
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"Unknown", /* 0xbb */
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"Optima", /* 0xbc */
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"Optima", /* 0xbc */
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"Optima Prime", /* 0xbd */
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"OptimaEEE", /* 0xbd */
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"Optima 2", /* 0xbe */
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"Optima 2", /* 0xbe */
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};
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};
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@ -23,6 +23,7 @@ enum {
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PSM_CONFIG_REG3 = 0x164,
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PSM_CONFIG_REG3 = 0x164,
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PSM_CONFIG_REG4 = 0x168,
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PSM_CONFIG_REG4 = 0x168,
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PCI_LDO_CTRL = 0xbc,
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};
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};
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/* Yukon-2 */
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/* Yukon-2 */
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@ -586,6 +587,10 @@ enum yukon_supr_rev {
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CHIP_REV_YU_SU_B1 = 3,
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CHIP_REV_YU_SU_B1 = 3,
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};
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};
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enum yukon_prm_rev {
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CHIP_REV_YU_PRM_Z1 = 1,
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CHIP_REV_YU_PRM_A0 = 2,
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};
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/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
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/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
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enum {
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enum {
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