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arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names
The macros for accessing fields in ID_AA64ISAR0_EL1 omit the _EL1 from the name of the register. In preparation for converting this register to be automatically generated update the names to include an _EL1, there should be no functional change. Signed-off-by: Mark Brown <broonie@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220503170233.507788-8-broonie@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Mark Brown
Catalin Marinas
parent
6329eb543d
commit
0eda2ec489
4 changed files with 66 additions and 66 deletions
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@ -142,7 +142,7 @@ static inline bool __init __early_cpu_has_rndr(void)
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{
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/* Open code as we run prior to the first call to cpufeature. */
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unsigned long ftr = read_sysreg_s(SYS_ID_AA64ISAR0_EL1);
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return (ftr >> ID_AA64ISAR0_RNDR_SHIFT) & 0xf;
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return (ftr >> ID_AA64ISAR0_EL1_RNDR_SHIFT) & 0xf;
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}
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static inline bool __init __must_check
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@ -740,23 +740,23 @@
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#define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
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/* id_aa64isar0 */
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#define ID_AA64ISAR0_RNDR_SHIFT 60
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#define ID_AA64ISAR0_TLB_SHIFT 56
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#define ID_AA64ISAR0_TS_SHIFT 52
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#define ID_AA64ISAR0_FHM_SHIFT 48
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#define ID_AA64ISAR0_DP_SHIFT 44
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#define ID_AA64ISAR0_SM4_SHIFT 40
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#define ID_AA64ISAR0_SM3_SHIFT 36
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#define ID_AA64ISAR0_SHA3_SHIFT 32
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#define ID_AA64ISAR0_RDM_SHIFT 28
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#define ID_AA64ISAR0_ATOMIC_SHIFT 20
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#define ID_AA64ISAR0_CRC32_SHIFT 16
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#define ID_AA64ISAR0_SHA2_SHIFT 12
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#define ID_AA64ISAR0_SHA1_SHIFT 8
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#define ID_AA64ISAR0_AES_SHIFT 4
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#define ID_AA64ISAR0_EL1_RNDR_SHIFT 60
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#define ID_AA64ISAR0_EL1_TLB_SHIFT 56
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#define ID_AA64ISAR0_EL1_TS_SHIFT 52
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#define ID_AA64ISAR0_EL1_FHM_SHIFT 48
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#define ID_AA64ISAR0_EL1_DP_SHIFT 44
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#define ID_AA64ISAR0_EL1_SM4_SHIFT 40
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#define ID_AA64ISAR0_EL1_SM3_SHIFT 36
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#define ID_AA64ISAR0_EL1_SHA3_SHIFT 32
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#define ID_AA64ISAR0_EL1_RDM_SHIFT 28
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#define ID_AA64ISAR0_EL1_ATOMIC_SHIFT 20
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#define ID_AA64ISAR0_EL1_CRC32_SHIFT 16
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#define ID_AA64ISAR0_EL1_SHA2_SHIFT 12
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#define ID_AA64ISAR0_EL1_SHA1_SHIFT 8
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#define ID_AA64ISAR0_EL1_AES_SHIFT 4
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#define ID_AA64ISAR0_TLB_RANGE_NI 0x0
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#define ID_AA64ISAR0_TLB_RANGE 0x2
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#define ID_AA64ISAR0_EL1_TLB_RANGE_NI 0x0
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#define ID_AA64ISAR0_EL1_TLB_RANGE 0x2
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/* id_aa64isar1 */
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#define ID_AA64ISAR1_I8MM_SHIFT 52
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@ -191,20 +191,20 @@ static bool __system_matches_cap(unsigned int n);
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* sync with the documentation of the CPU feature register ABI.
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*/
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static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMIC_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0),
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ARM64_FTR_END,
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};
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@ -2013,7 +2013,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.type = ARM64_CPUCAP_SYSTEM_FEATURE,
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.matches = has_cpuid_feature,
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.sys_reg = SYS_ID_AA64ISAR0_EL1,
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.field_pos = ID_AA64ISAR0_ATOMIC_SHIFT,
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.field_pos = ID_AA64ISAR0_EL1_ATOMIC_SHIFT,
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.field_width = 4,
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.sign = FTR_UNSIGNED,
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.min_field_value = 2,
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@ -2195,10 +2195,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.type = ARM64_CPUCAP_SYSTEM_FEATURE,
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.matches = has_cpuid_feature,
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.sys_reg = SYS_ID_AA64ISAR0_EL1,
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.field_pos = ID_AA64ISAR0_TLB_SHIFT,
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.field_pos = ID_AA64ISAR0_EL1_TLB_SHIFT,
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.field_width = 4,
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.sign = FTR_UNSIGNED,
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.min_field_value = ID_AA64ISAR0_TLB_RANGE,
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.min_field_value = ID_AA64ISAR0_EL1_TLB_RANGE,
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},
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#ifdef CONFIG_ARM64_HW_AFDBM
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{
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@ -2227,7 +2227,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.type = ARM64_CPUCAP_SYSTEM_FEATURE,
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.matches = has_cpuid_feature,
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.sys_reg = SYS_ID_AA64ISAR0_EL1,
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.field_pos = ID_AA64ISAR0_CRC32_SHIFT,
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.field_pos = ID_AA64ISAR0_EL1_CRC32_SHIFT,
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.field_width = 4,
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.min_field_value = 1,
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},
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@ -2382,7 +2382,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.type = ARM64_CPUCAP_SYSTEM_FEATURE,
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.matches = has_cpuid_feature,
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.sys_reg = SYS_ID_AA64ISAR0_EL1,
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.field_pos = ID_AA64ISAR0_RNDR_SHIFT,
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.field_pos = ID_AA64ISAR0_EL1_RNDR_SHIFT,
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.field_width = 4,
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.sign = FTR_UNSIGNED,
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.min_field_value = 1,
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@ -2514,22 +2514,22 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
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#endif
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static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
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HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
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HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
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HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
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HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
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@ -159,20 +159,20 @@
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* No restrictions on instructions implemented in AArch64.
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*/
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#define PVM_ID_AA64ISAR0_ALLOW (\
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ARM64_FEATURE_MASK(ID_AA64ISAR0_AES) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA1) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA2) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_CRC32) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_ATOMIC) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_RDM) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA3) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_SM3) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_SM4) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_DP) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_FHM) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_TS) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_TLB) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_RNDR) \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_AES) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA1) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA2) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_CRC32) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_ATOMIC) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RDM) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA3) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM3) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM4) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_DP) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_FHM) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TS) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TLB) | \
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ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RNDR) \
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)
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#define PVM_ID_AA64ISAR1_ALLOW (\
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