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MIPS changes for v4.11 

Miscellaneous:
  - Add IRQ stacks
  - Add cacheinfo support
  - Add "uzImage.bin" zboot target
  - Unify performance counter definitions
  - Export various (mainly assembly) symbols alongside their
    definitions
  - Audit and remove unnecessary uses of module.h
 
 kexec & kdump:
  - Lots of improvements and fixes
  - Add correct copy_regs implementations
  - Add debug logging of new kernel information
 
 Security:
  - Use Makefile.postlink to insert relocations into vmlinux
  - Provide plat_post_relocation hook (used for Octeon KASLR)
  - Add support for tuning mmap randomisation
  - Relocate DTB
 
 microMIPS:
  - A load of unwind fixes
  - Add some missing .insn to fix link errors
 
 MIPSr6:
  - Fix MULTU/MADDU/MSUBU sign extension in r2 emulation
  - Remove r2_emul_return and use ERETNC unconditionally on MIPSr6
  - Allow pre-r6 emulation on SMP MIPSr6 kernels
 
 Cache management:
  - Treat physically indexed dcache as non-aliasing
  - Add return errors to protected cache ops for KVM
  - CM3: Ensure L1 & L2 cache ECC checking matches
  - CM3: Indicate inclusive caches
  - I6400: Treat dcache as physically indexed
 
 Memory management:
  - Ensure bootmem doesn't corrupt reserved memory
  - Export some TLB exception generation functions for KVM
 
 OF
  - NULL check initial_boot_params before use in of_scan_flat_dt()
  - Fix unaligned access in of_alias_scan()
 
 SMP:
  - CPS: Don't BUG if a CPU fails to start
 
 Other fixes
  - Fix longstanding 64-bit IP checksum carry bug
  - Fix KERN_CONT fallout in cpu-bugs64.c and sync-r4k.c
  - Update defconfigs for NF_CT_PROTO_DCCP, DPLITE,
    CPU_FREQ_STAT,SCSI_DH changes
  - Disable certain builtin compiler options, stack-check (whole
    kernel), asynchronous-unwind-tables (VDSO).
  - A bunch of build fixes from kernelci.org testing
  - Various other minor cleanups & corrections
 
 BMIPS:
  - Migrate interrupts during bmips_cpu_disable
  - BCM47xx: Add Luxul devices
  - BCM47xx: Fix Asus WL-500W button inversion
  - BCM7xxx: Add SPI device nodes
 
 Generic (multiplatform):
  - Add kexec DTB passing
  - Fix big endian
  - Add cpp_its_S in ksym_dep_filter to silence build warning
 
 IP22:
  - Reformat inline assembler code to modern standards
  - Fix binutils 2.25 build error
 
 IP27:
  - Fix duplicate CAC_BASE definition build error
  - Disable qlge driver to workaround broken compiler
 
 Lantiq:
  - Refresh defconfig and activate more drivers
  - Lock DMA register access
  - Fix cascading IRQ setup
  - Fix build of VPE loader
  - xway: Fix ethernet packet header corruption over reboot
 
 Loongson1
  - Add watchdog support
  - 1B: Reduce DEFAULT_MEMSIZE to 64MB
  - 1B: Change OSC clock name to match rest of kernel
  - 1C: Remove ARCH_WANT_OPTIONAL_GPIOLIB
 
 Octeon:
  - Add KASLR support
  - Support Octeon III USB controller
  - Fix large copy_from_user corner case
  - Enable devtmpfs in defconfig
 
 Netlogic:
  - Fix non-default XLR build error due to netlogic,xlp-pic code
  - Fix assembler warning from smpboot.S
 
 pic32mzda:
  - Fix linker error when early printk is disabled
 
 Pistachio:
  - Add base device tree
  - Add Ci40 "Marduk" device tree
 
 Ralink:
  - Support raw appended DTB
  - Add missing I2C & I2S clocks
  - Add missing pinmux and fix pinmux function name typo
  - Add missing clk_round_rate()
  - Clean up prom_init()
  - MT7621: Set SoC type
  - MT7621: Support highmem
 
 TXx9:
  - Modernize printing of kernel messages and resolve KERN_CONT fallout
  - 7segled: use permission-specific DEVICE_ATTR variants
 
 XilFPGA:
  - Add IRQ controller and UART IRQ
  - Add AXI I2C and emaclite to DT & defconfig
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Merge tag 'mips_4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips

Pull MIPS updates from James Hogan:
 "Here's the main MIPS pull request for 4.11.

  It contains a few new features such as IRQ stacks, cacheinfo support,
  and KASLR for Octeon CPUs, and a variety of smaller improvements and
  fixes including devicetree additions, kexec cleanups, microMIPS stack
  unwinding fixes, and a bunch of build fixes to clean up continuous
  integration builds.

  Its all been in linux-next for at least a couple of days, most of it
  far longer.

  Miscellaneous:
   - Add IRQ stacks
   - Add cacheinfo support
   - Add "uzImage.bin" zboot target
   - Unify performance counter definitions
   - Export various (mainly assembly) symbols alongside their
     definitions
   - Audit and remove unnecessary uses of module.h

  kexec & kdump:
   - Lots of improvements and fixes
   - Add correct copy_regs implementations
   - Add debug logging of new kernel information

  Security:
   - Use Makefile.postlink to insert relocations into vmlinux
   - Provide plat_post_relocation hook (used for Octeon KASLR)
   - Add support for tuning mmap randomisation
   - Relocate DTB

  microMIPS:
   - A load of unwind fixes
   - Add some missing .insn to fix link errors

  MIPSr6:
   - Fix MULTU/MADDU/MSUBU sign extension in r2 emulation
   - Remove r2_emul_return and use ERETNC unconditionally on MIPSr6
   - Allow pre-r6 emulation on SMP MIPSr6 kernels

  Cache management:
   - Treat physically indexed dcache as non-aliasing
   - Add return errors to protected cache ops for KVM
   - CM3: Ensure L1 & L2 cache ECC checking matches
   - CM3: Indicate inclusive caches
   - I6400: Treat dcache as physically indexed

  Memory management:
   - Ensure bootmem doesn't corrupt reserved memory
   - Export some TLB exception generation functions for KVM

  OF:
   - NULL check initial_boot_params before use in of_scan_flat_dt()
   - Fix unaligned access in of_alias_scan()

  SMP:
   - CPS: Don't BUG if a CPU fails to start

  Other fixes:
   - Fix longstanding 64-bit IP checksum carry bug
   - Fix KERN_CONT fallout in cpu-bugs64.c and sync-r4k.c
   - Update defconfigs for NF_CT_PROTO_DCCP, DPLITE,
     CPU_FREQ_STAT,SCSI_DH changes
   - Disable certain builtin compiler options, stack-check (whole
     kernel), asynchronous-unwind-tables (VDSO).
   - A bunch of build fixes from kernelci.org testing
   - Various other minor cleanups & corrections

  BMIPS:
   - Migrate interrupts during bmips_cpu_disable
   - BCM47xx: Add Luxul devices
   - BCM47xx: Fix Asus WL-500W button inversion
   - BCM7xxx: Add SPI device nodes

  Generic (multiplatform):
   - Add kexec DTB passing
   - Fix big endian
   - Add cpp_its_S in ksym_dep_filter to silence build warning

  IP22:
   - Reformat inline assembler code to modern standards
   - Fix binutils 2.25 build error

  IP27:
   - Fix duplicate CAC_BASE definition build error
   - Disable qlge driver to workaround broken compiler

  Lantiq:
   - Refresh defconfig and activate more drivers
   - Lock DMA register access
   - Fix cascading IRQ setup
   - Fix build of VPE loader
   - xway: Fix ethernet packet header corruption over reboot

  Loongson1
   - Add watchdog support
   - 1B: Reduce DEFAULT_MEMSIZE to 64MB
   - 1B: Change OSC clock name to match rest of kernel
   - 1C: Remove ARCH_WANT_OPTIONAL_GPIOLIB

  Octeon:
   - Add KASLR support
   - Support Octeon III USB controller
   - Fix large copy_from_user corner case
   - Enable devtmpfs in defconfig

  Netlogic:
   - Fix non-default XLR build error due to netlogic,xlp-pic code
   - Fix assembler warning from smpboot.S

  pic32mzda:
   - Fix linker error when early printk is disabled

  Pistachio:
   - Add base device tree
   - Add Ci40 "Marduk" device tree

  Ralink:
   - Support raw appended DTB
   - Add missing I2C & I2S clocks
   - Add missing pinmux and fix pinmux function name typo
   - Add missing clk_round_rate()
   - Clean up prom_init()
   - MT7621: Set SoC type
   - MT7621: Support highmem

  TXx9:
   - Modernize printing of kernel messages and resolve KERN_CONT fallout
   - 7segled: use permission-specific DEVICE_ATTR variants

  XilFPGA:
   - Add IRQ controller and UART IRQ
   - Add AXI I2C and emaclite to DT & defconfig"

* tag 'mips_4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: (148 commits)
  MIPS: VDSO: Explicitly use -fno-asynchronous-unwind-tables
  MIPS: BCM47XX: Fix button inversion for Asus WL-500W
  MIPS: DTS: Add img directory to Makefile
  MIPS: ip27: Disable qlge driver in defconfig
  MIPS: pic32mzda: Fix linker error for pic32_get_pbclk()
  MIPS: Lantiq: Keep ethernet enabled during boot
  MIPS: OCTEON: Fix copy_from_user fault handling for large buffers
  MIPS: Fix special case in 64 bit IP checksumming.
  MIPS: OCTEON: Enable DEVTMPFS
  MIPS: lantiq: Set physical_memsize
  MIPS: sysmips: Remove duplicated include from syscall.c
  Kbuild: Add cpp_its_S in ksym_dep_filter
  MIPS: Audit and remove any unnecessary uses of module.h
  MIPS: Unify perf counter register definitions
  MIPS: Disable stack checks on MIPS kernels
  MIPS: OCTEON: Platform support for OCTEON III USB controller
  MIPS: Lantiq: Fix cascaded IRQ setup
  MIPS: sync-r4k: Fix KERN_CONT fallout
  MIPS: IRQ Stack: Fix erroneous jal to plat_irq_dispatch
  MIPS: Fix distclean with Makefile.postlink
  ...
This commit is contained in:
Linus Torvalds 2017-02-21 14:21:11 -08:00
parent 252b95c0ed cfd75c2db1
commit 0f002fddbe
253 changed files with 4089 additions and 1028 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
Documentation/devicetree/bindings/mips/img/pistachio-marduk.txt Normal file
View File

@ -0,0 +1,10 @@
Imagination Technologies' Pistachio SoC based Marduk Board
==========================================================
Compatible string must be "img,pistachio-marduk", "img,pistachio"
Hardware and other related documentation is available at
https://docs.creatordev.io/ci40/
It is also known as Creator Ci40. Marduk is legacy name and will
be there for decades.

8
MAINTAINERS
View File

@ -7707,6 +7707,12 @@ W: http://www.kernel.org/doc/man-pages
L: linux-man@vger.kernel.org
S: Maintained
MARDUK (CREATOR CI40) DEVICE TREE SUPPORT
M: Rahul Bedarkar <rahul.bedarkar@imgtec.com>
L: linux-mips@linux-mips.org
S: Maintained
F: arch/mips/boot/dts/img/pistachio_marduk.dts
MARVELL 88E6XXX ETHERNET SWITCH FABRIC DRIVER
M: Andrew Lunn <andrew@lunn.ch>
M: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
@ -9795,7 +9801,7 @@ L: linux-mips@linux-mips.org
S: Maintained
F: arch/mips/pistachio/
F: arch/mips/include/asm/mach-pistachio/
F: arch/mips/boot/dts/pistachio/
F: arch/mips/boot/dts/img/pistachio*
F: arch/mips/configs/pistachio*_defconfig
PKTCDVD DRIVER

27
arch/mips/Kconfig
View File

@ -9,10 +9,13 @@ config MIPS
select HAVE_CONTEXT_TRACKING
select HAVE_GENERIC_DMA_COHERENT
select HAVE_IDE
select HAVE_IRQ_EXIT_ON_IRQ_STACK
select HAVE_OPROFILE
select HAVE_PERF_EVENTS
select PERF_USE_VMALLOC
select HAVE_ARCH_KGDB
select HAVE_ARCH_MMAP_RND_BITS if MMU
select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
select HAVE_ARCH_SECCOMP_FILTER
select HAVE_ARCH_TRACEHOOK
select HAVE_CBPF_JIT if !CPU_MICROMIPS
@ -94,6 +97,7 @@ config MIPS_GENERIC
select PCI_DRIVERS_GENERIC
select PINCTRL
select SMP_UP if SMP
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
select SYS_HAS_CPU_MIPS32_R2
select SYS_HAS_CPU_MIPS32_R6
@ -478,6 +482,7 @@ config MACH_XILFPGA
select SYS_SUPPORTS_ZBOOT_UART16550
select USE_OF
select USE_GENERIC_EARLY_PRINTK_8250
select XILINX_INTC
help
This enables support for the IMG University Program MIPSfpga platform.
@ -909,6 +914,7 @@ config CAVIUM_OCTEON_SOC
select NR_CPUS_DEFAULT_16
select BUILTIN_DTB
select MTD_COMPLEX_MAPPINGS
select SYS_SUPPORTS_RELOCATABLE
help
This option supports all of the Octeon reference boards from Cavium
Networks. It builds a kernel that dynamically determines the Octeon
@ -1427,7 +1433,6 @@ config CPU_LOONGSON1C
bool "Loongson 1C"
depends on SYS_HAS_CPU_LOONGSON1C
select CPU_LOONGSON1
select ARCH_WANT_OPTIONAL_GPIOLIB
select LEDS_GPIO_REGISTER
help
The Loongson 1C is a 32-bit SoC, which implements the MIPS32
@ -2288,7 +2293,7 @@ config MIPS_MT_FPAFF
config MIPSR2_TO_R6_EMULATOR
bool "MIPS R2-to-R6 emulator"
depends on CPU_MIPSR6 && !SMP
depends on CPU_MIPSR6
default y
help
Choose this option if you want to run non-R6 MIPS userland code.
@ -2296,8 +2301,6 @@ config MIPSR2_TO_R6_EMULATOR
default. You can enable it using the 'mipsr2emu' kernel option.
The only reason this is a build-time option is to save ~14K from the
final kernel image.
comment "MIPS R2-to-R6 emulator is only available for UP kernels"
depends on SMP && CPU_MIPSR6
config MIPS_VPE_LOADER
bool "VPE loader support."
@ -2572,7 +2575,7 @@ config SYS_SUPPORTS_NUMA
config RELOCATABLE
bool "Relocatable kernel"
depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6)
depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC)
help
This builds a kernel image that retains relocation information
so it can be loaded someplace besides the default 1MB.
@ -3075,6 +3078,20 @@ config MMU
bool
default y
config ARCH_MMAP_RND_BITS_MIN
default 12 if 64BIT
default 8
config ARCH_MMAP_RND_BITS_MAX
default 18 if 64BIT
default 15
config ARCH_MMAP_RND_COMPAT_BITS_MIN
default 8
config ARCH_MMAP_RND_COMPAT_BITS_MAX
default 15
config I8253
bool
select CLKSRC_I8253

35
arch/mips/Makefile
View File

@ -131,6 +131,21 @@ cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.
cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
-fno-omit-frame-pointer
# Some distribution-specific toolchains might pass the -fstack-check
# option during the build, which adds a simple stack-probe at the beginning
# of every function. This stack probe is to ensure that there is enough
# stack space, else a SEGV is generated. This is not desirable for MIPS
# as kernel stacks are small, placed in unmapped virtual memory, and do not
# grow when overflowed. Especially on SGI IP27 platforms, this check will
# lead to a NULL pointer dereference in _raw_spin_lock_irq.
#
# In disassembly, this stack probe appears at the top of a function as:
# sd zero,<offset>(sp)
# Where <offset> is a negative value.
#
cflags-y += -fno-stack-check
#
# CPU-dependent compiler/assembler options for optimization.
#
@ -320,6 +335,9 @@ bootz-y := vmlinuz
bootz-y += vmlinuz.bin
bootz-y += vmlinuz.ecoff
bootz-y += vmlinuz.srec
ifeq ($(shell expr $(zload-y) \< 0xffffffff80000000 2> /dev/null), 0)
bootz-y += uzImage.bin
endif
ifdef CONFIG_LASAT
rom.bin rom.sw: vmlinux
@ -327,10 +345,6 @@ rom.bin rom.sw: vmlinux
$(bootvars-y) $@
endif
CMD_RELOCS = arch/mips/boot/tools/relocs
quiet_cmd_relocs = RELOCS $<
cmd_relocs = $(CMD_RELOCS) $<
#
# Some machines like the Indy need 32-bit ELF binaries for booting purposes.
# Other need ECOFF, so we build a 32-bit ELF binary for them which we then
@ -339,11 +353,6 @@ quiet_cmd_relocs = RELOCS $<
quiet_cmd_32 = OBJCOPY $@
cmd_32 = $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
vmlinux.32: vmlinux
ifeq ($(CONFIG_RELOCATABLE)$(CONFIG_64BIT),yy)
# Currently, objcopy fails to handle the relocations in the elf64
# So the relocs tool must be run here to remove them first
$(call cmd,relocs)
endif
$(call cmd,32)
#
@ -359,9 +368,6 @@ all: $(all-y)
# boot
$(boot-y): $(vmlinux-32) FORCE
ifeq ($(CONFIG_RELOCATABLE)$(CONFIG_32BIT),yy)
$(call cmd,relocs)
endif
$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) \
$(bootvars-y) arch/mips/boot/$@
@ -395,11 +401,11 @@ dtbs_install:
archprepare:
ifdef CONFIG_MIPS32_N32
@echo ' Checking missing-syscalls for N32'
@$(kecho) ' Checking missing-syscalls for N32'
$(Q)$(MAKE) $(build)=. missing-syscalls missing_syscalls_flags="-mabi=n32"
endif
ifdef CONFIG_MIPS32_O32
@echo ' Checking missing-syscalls for O32'
@$(kecho) ' Checking missing-syscalls for O32'
$(Q)$(MAKE) $(build)=. missing-syscalls missing_syscalls_flags="-mabi=32"
endif
@ -433,6 +439,7 @@ define archhelp
echo ' uImage.gz - U-Boot image (gzip)'
echo ' uImage.lzma - U-Boot image (lzma)'
echo ' uImage.lzo - U-Boot image (lzo)'
echo ' uzImage.bin - U-Boot image (self-extracting)'
echo ' dtbs - Device-tree blobs for enabled boards'
echo ' dtbs_install - Install dtbs to $(INSTALL_DTBS_PATH)'
echo

35
arch/mips/Makefile.postlink Normal file
View File

@ -0,0 +1,35 @@
# ===========================================================================
# Post-link MIPS pass
# ===========================================================================
#
# 1. Insert relocations into vmlinux
PHONY := __archpost
__archpost:
-include include/config/auto.conf
include scripts/Kbuild.include
CMD_RELOCS = arch/mips/boot/tools/relocs
quiet_cmd_relocs = RELOCS $@
cmd_relocs = $(CMD_RELOCS) $@
# `@true` prevents complaint when there is nothing to be done
vmlinux: FORCE
@true
ifeq ($(CONFIG_RELOCATABLE),y)
$(call if_changed,relocs)
endif
%.ko: FORCE
@true
clean:
@true
PHONY += FORCE clean
FORCE:
.PHONY: $(PHONY)

1
arch/mips/alchemy/board-gpr.c
View File

@ -236,7 +236,6 @@ static struct platform_device gpr_i2c_device = {
static struct i2c_board_info gpr_i2c_info[] __initdata = {
{
I2C_BOARD_INFO("lm83", 0x18),
.type = "lm83"
}
};

2
arch/mips/alchemy/common/dbdma.c
View File

@ -35,7 +35,7 @@
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/syscore_ops.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1xxx_dbdma.h>

2
arch/mips/alchemy/common/dma.c
View File

@ -31,7 +31,7 @@
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/spinlock.h>

1
arch/mips/alchemy/common/gpiolib.c
View File

@ -32,7 +32,6 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/gpio.h>
#include <asm/mach-au1x00/gpio-au1000.h>

1
arch/mips/alchemy/common/prom.c
View File

@ -33,7 +33,6 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/string.h>

2
arch/mips/alchemy/common/usb.c
View File

@ -10,9 +10,9 @@
*/
#include <linux/clk.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/syscore_ops.h>
#include <asm/cpu.h>

2
arch/mips/alchemy/common/vss.c
View File

@ -6,7 +6,7 @@
* for various media blocks are enabled/disabled.
*/
#include <linux/module.h>
#include <linux/export.h>
#include <linux/spinlock.h>
#include <asm/mach-au1x00/au1000.h>

3
arch/mips/alchemy/devboards/bcsr.c
View File

@ -9,7 +9,8 @@
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <asm/addrspace.h>

2
arch/mips/ar7/clock.c
View File

@ -21,7 +21,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/delay.h>
#include <linux/gcd.h>
#include <linux/io.h>

3
arch/mips/ar7/gpio.c
View File

@ -18,7 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/gpio.h>
#include <asm/mach-ar7/ar7.h>

1
arch/mips/ar7/memory.c
View File

@ -19,7 +19,6 @@
#include <linux/bootmem.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/pfn.h>
#include <linux/proc_fs.h>
#include <linux/string.h>

1
arch/mips/ar7/platform.c
View File

@ -19,7 +19,6 @@
#include <linux/init.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>

2
arch/mips/ar7/prom.c
View File

@ -21,7 +21,7 @@
#include <linux/kernel.h>
#include <linux/serial_reg.h>
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/string.h>
#include <linux/io.h>
#include <asm/bootinfo.h>

10
arch/mips/ath79/clock.c
View File

@ -12,7 +12,6 @@
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
@ -45,7 +44,7 @@ static struct clk *__init ath79_add_sys_clkdev(
int err;
clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
if (!clk)
if (IS_ERR(clk))
panic("failed to allocate %s clock structure", id);
err = clk_register_clkdev(clk, id, NULL);
@ -508,16 +507,19 @@ static void __init ath79_clocks_init_dt_ng(struct device_node *np)
ar9330_clk_init(ref_clk, pll_base);
else {
pr_err("%s: could not find any appropriate clk_init()\n", dnfn);
goto err_clk;
goto err_iounmap;
}
if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
pr_err("%s: could not register clk provider\n", dnfn);
goto err_clk;
goto err_iounmap;
}
return;
err_iounmap:
iounmap(pll_base);
err_clk:
clk_put(ref_clk);

2
arch/mips/ath79/common.c
View File

@ -13,7 +13,7 @@
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/types.h>
#include <linux/spinlock.h>

9
arch/mips/bcm47xx/board.c
View File

@ -149,6 +149,15 @@ struct bcm47xx_board_type_list2 bcm47xx_board_list_boot_hw[] __initconst = {
/* board_id */
static const
struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = {
{{BCM47XX_BOARD_LUXUL_ABR_4400_V1, "Luxul ABR-4400 V1"}, "luxul_abr4400_v1"},
{{BCM47XX_BOARD_LUXUL_XAP_310_V1, "Luxul XAP-310 V1"}, "luxul_xap310_v1"},
{{BCM47XX_BOARD_LUXUL_XAP_1210_V1, "Luxul XAP-1210 V1"}, "luxul_xap1210_v1"},
{{BCM47XX_BOARD_LUXUL_XAP_1230_V1, "Luxul XAP-1230 V1"}, "luxul_xap1230_v1"},
{{BCM47XX_BOARD_LUXUL_XAP_1240_V1, "Luxul XAP-1240 V1"}, "luxul_xap1240_v1"},
{{BCM47XX_BOARD_LUXUL_XAP_1500_V1, "Luxul XAP-1500 V1"}, "luxul_xap1500_v1"},
{{BCM47XX_BOARD_LUXUL_XBR_4400_V1, "Luxul XBR-4400 V1"}, "luxul_xbr4400_v1"},
{{BCM47XX_BOARD_LUXUL_XVW_P30_V1, "Luxul XVW-P30 V1"}, "luxul_xvwp30_v1"},
{{BCM47XX_BOARD_LUXUL_XWR_600_V1, "Luxul XWR-600 V1"}, "luxul_xwr600_v1"},
{{BCM47XX_BOARD_LUXUL_XWR_1750_V1, "Luxul XWR-1750 V1"}, "luxul_xwr1750_v1"},
{{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"},
{{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"},

82
arch/mips/bcm47xx/buttons.c
View File

@ -17,6 +17,12 @@
.active_low = 1, \
}
#define BCM47XX_GPIO_KEY_H(_gpio, _code) \
{ \
.code = _code, \
.gpio = _gpio, \
}
/* Asus */
static const struct gpio_keys_button
@ -79,8 +85,8 @@ bcm47xx_buttons_asus_wl500gpv2[] __initconst = {
static const struct gpio_keys_button
bcm47xx_buttons_asus_wl500w[] __initconst = {
BCM47XX_GPIO_KEY(6, KEY_RESTART),
BCM47XX_GPIO_KEY(7, KEY_WPS_BUTTON),
BCM47XX_GPIO_KEY_H(6, KEY_RESTART),
BCM47XX_GPIO_KEY_H(7, KEY_WPS_BUTTON),
};
static const struct gpio_keys_button
@ -301,6 +307,51 @@ bcm47xx_buttons_linksys_wrtsl54gs[] __initconst = {
/* Luxul */
static const struct gpio_keys_button
bcm47xx_buttons_luxul_abr_4400_v1[] = {
BCM47XX_GPIO_KEY(14, KEY_RESTART),
};
static const struct gpio_keys_button
bcm47xx_buttons_luxul_xap_310_v1[] = {
BCM47XX_GPIO_KEY(20, KEY_RESTART),
};
static const struct gpio_keys_button
bcm47xx_buttons_luxul_xap_1210_v1[] = {
BCM47XX_GPIO_KEY(8, KEY_RESTART),
};
static const struct gpio_keys_button
bcm47xx_buttons_luxul_xap_1230_v1[] = {
BCM47XX_GPIO_KEY(8, KEY_RESTART),
};
static const struct gpio_keys_button
bcm47xx_buttons_luxul_xap_1240_v1[] = {
BCM47XX_GPIO_KEY(8, KEY_RESTART),
};
static const struct gpio_keys_button
bcm47xx_buttons_luxul_xap_1500_v1[] = {
BCM47XX_GPIO_KEY(14, KEY_RESTART),
};
static const struct gpio_keys_button
bcm47xx_buttons_luxul_xbr_4400_v1[] = {
BCM47XX_GPIO_KEY(14, KEY_RESTART),
};
static const struct gpio_keys_button
bcm47xx_buttons_luxul_xvw_p30_v1[] = {
BCM47XX_GPIO_KEY(20, KEY_RESTART),
};
static const struct gpio_keys_button
bcm47xx_buttons_luxul_xwr_600_v1[] = {
BCM47XX_GPIO_KEY(8, KEY_RESTART),
};
static const struct gpio_keys_button
bcm47xx_buttons_luxul_xwr_1750_v1[] = {
BCM47XX_GPIO_KEY(14, BTN_TASK),
@ -561,6 +612,33 @@ int __init bcm47xx_buttons_register(void)
err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrtsl54gs);
break;
case BCM47XX_BOARD_LUXUL_ABR_4400_V1:
err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_abr_4400_v1);
break;
case BCM47XX_BOARD_LUXUL_XAP_310_V1:
err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xap_310_v1);
break;
case BCM47XX_BOARD_LUXUL_XAP_1210_V1:
err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xap_1210_v1);
break;
case BCM47XX_BOARD_LUXUL_XAP_1230_V1:
err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xap_1230_v1);
break;
case BCM47XX_BOARD_LUXUL_XAP_1240_V1:
err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xap_1240_v1);
break;
case BCM47XX_BOARD_LUXUL_XAP_1500_V1:
err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xap_1500_v1);
break;
case BCM47XX_BOARD_LUXUL_XBR_4400_V1:
err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xbr_4400_v1);
break;
case BCM47XX_BOARD_LUXUL_XVW_P30_V1:
err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xvw_p30_v1);
break;
case BCM47XX_BOARD_LUXUL_XWR_600_V1:
err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xwr_600_v1);
break;
case BCM47XX_BOARD_LUXUL_XWR_1750_V1:
err = bcm47xx_copy_bdata(bcm47xx_buttons_luxul_xwr_1750_v1);
break;

81
arch/mips/bcm47xx/leds.c
View File

@ -372,6 +372,60 @@ bcm47xx_leds_linksys_wrtsl54gs[] __initconst = {
/* Luxul */
static const struct gpio_led
bcm47xx_leds_luxul_abr_4400_v1[] __initconst = {
BCM47XX_GPIO_LED(12, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
BCM47XX_GPIO_LED_TRIGGER(15, "green", "status", 0, "timer"),
};
static const struct gpio_led
bcm47xx_leds_luxul_xap_310_v1[] __initconst = {
BCM47XX_GPIO_LED_TRIGGER(6, "green", "status", 1, "timer"),
};
static const struct gpio_led
bcm47xx_leds_luxul_xap_1210_v1[] __initconst = {
BCM47XX_GPIO_LED_TRIGGER(6, "green", "status", 1, "timer"),
};
static const struct gpio_led
bcm47xx_leds_luxul_xap_1230_v1[] __initconst = {
BCM47XX_GPIO_LED(3, "blue", "2ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
BCM47XX_GPIO_LED(4, "green", "bridge", 0, LEDS_GPIO_DEFSTATE_OFF),
BCM47XX_GPIO_LED_TRIGGER(6, "green", "status", 1, "timer"),
};
static const struct gpio_led
bcm47xx_leds_luxul_xap_1240_v1[] __initconst = {
BCM47XX_GPIO_LED(3, "blue", "2ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
BCM47XX_GPIO_LED(4, "green", "bridge", 0, LEDS_GPIO_DEFSTATE_OFF),
BCM47XX_GPIO_LED_TRIGGER(6, "green", "status", 1, "timer"),
};
static const struct gpio_led
bcm47xx_leds_luxul_xap_1500_v1[] __initconst = {
BCM47XX_GPIO_LED_TRIGGER(13, "green", "status", 1, "timer"),
};
static const struct gpio_led
bcm47xx_leds_luxul_xbr_4400_v1[] __initconst = {
BCM47XX_GPIO_LED(12, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
BCM47XX_GPIO_LED_TRIGGER(15, "green", "status", 0, "timer"),
};
static const struct gpio_led
bcm47xx_leds_luxul_xvw_p30_v1[] __initconst = {
BCM47XX_GPIO_LED_TRIGGER(0, "blue", "status", 1, "timer"),
BCM47XX_GPIO_LED(1, "green", "link", 1, LEDS_GPIO_DEFSTATE_OFF),
};
static const struct gpio_led
bcm47xx_leds_luxul_xwr_600_v1[] __initconst = {
BCM47XX_GPIO_LED(3, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
BCM47XX_GPIO_LED_TRIGGER(6, "green", "status", 1, "timer"),
BCM47XX_GPIO_LED(9, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
};
static const struct gpio_led
bcm47xx_leds_luxul_xwr_1750_v1[] __initconst = {
BCM47XX_GPIO_LED(5, "green", "5ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
@ -633,6 +687,33 @@ void __init bcm47xx_leds_register(void)
bcm47xx_set_pdata(bcm47xx_leds_linksys_wrtsl54gs);
break;
case BCM47XX_BOARD_LUXUL_ABR_4400_V1:
bcm47xx_set_pdata(bcm47xx_leds_luxul_abr_4400_v1);
break;
case BCM47XX_BOARD_LUXUL_XAP_310_V1:
bcm47xx_set_pdata(bcm47xx_leds_luxul_xap_310_v1);
break;
case BCM47XX_BOARD_LUXUL_XAP_1210_V1:
bcm47xx_set_pdata(bcm47xx_leds_luxul_xap_1210_v1);
break;
case BCM47XX_BOARD_LUXUL_XAP_1230_V1:
bcm47xx_set_pdata(bcm47xx_leds_luxul_xap_1230_v1);
break;
case BCM47XX_BOARD_LUXUL_XAP_1240_V1:
bcm47xx_set_pdata(bcm47xx_leds_luxul_xap_1240_v1);
break;
case BCM47XX_BOARD_LUXUL_XAP_1500_V1:
bcm47xx_set_pdata(bcm47xx_leds_luxul_xap_1500_v1);
break;
case BCM47XX_BOARD_LUXUL_XBR_4400_V1:
bcm47xx_set_pdata(bcm47xx_leds_luxul_xbr_4400_v1);
break;
case BCM47XX_BOARD_LUXUL_XVW_P30_V1:
bcm47xx_set_pdata(bcm47xx_leds_luxul_xvw_p30_v1);
break;
case BCM47XX_BOARD_LUXUL_XWR_600_V1:
bcm47xx_set_pdata(bcm47xx_leds_luxul_xwr_600_v1);
break;
case BCM47XX_BOARD_LUXUL_XWR_1750_V1:
bcm47xx_set_pdata(bcm47xx_leds_luxul_xwr_1750_v1);
break;

3
arch/mips/bcm63xx/clk.c
View File

@ -6,7 +6,8 @@
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/clk.h>

2
arch/mips/bcm63xx/cpu.c
View File

@ -8,7 +8,7 @@
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/cpu.h>
#include <asm/cpu.h>
#include <asm/cpu-info.h>

3
arch/mips/bcm63xx/cs.c
View File

@ -7,7 +7,8 @@
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/spinlock.h>
#include <linux/log2.h>
#include <bcm63xx_cpu.h>

2
arch/mips/bcm63xx/gpio.c
View File

@ -8,7 +8,7 @@
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/gpio/driver.h>

1
arch/mips/bcm63xx/irq.c
View File

@ -10,7 +10,6 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/spinlock.h>
#include <asm/irq_cpu.h>

3
arch/mips/bcm63xx/reset.c
View File

@ -6,7 +6,8 @@
* Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/clk.h>

3
arch/mips/bcm63xx/timer.c
View File

@ -8,7 +8,8 @@
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/clk.h>

10
arch/mips/boot/compressed/Makefile
View File

@ -18,14 +18,14 @@ include $(srctree)/arch/mips/Kbuild.platforms
BOOT_HEAP_SIZE := 0x400000
# Disable Function Tracer
KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//")
KBUILD_CFLAGS := $(filter-out -pg, $(KBUILD_CFLAGS))
KBUILD_CFLAGS := $(filter-out -fstack-protector, $(KBUILD_CFLAGS))
KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \
KBUILD_CFLAGS := $(KBUILD_CFLAGS) -D__KERNEL__ \
-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull"
KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
KBUILD_AFLAGS := $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
-DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS)
@ -84,6 +84,7 @@ else
VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
$(obj)/vmlinux.bin $(VMLINUX_LOAD_ADDRESS))
endif
UIMAGE_LOADADDR = $(VMLINUZ_LOAD_ADDRESS)
vmlinuzobjs-y += $(obj)/piggy.o
@ -129,4 +130,7 @@ OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec
vmlinuz.srec: vmlinuz
$(call cmd,objcopy)
uzImage.bin: vmlinuz.bin FORCE
$(call if_changed,uimage,none)
clean-files := $(objtree)/vmlinuz $(objtree)/vmlinuz.{32,ecoff,bin,srec}

1
arch/mips/boot/dts/Makefile
View File

@ -1,5 +1,6 @@
dts-dirs += brcm
dts-dirs += cavium-octeon
dts-dirs += img
dts-dirs += ingenic
dts-dirs += lantiq
dts-dirs += mti

49
arch/mips/boot/dts/brcm/bcm7125.dtsi
View File

@ -91,15 +91,15 @@
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406780 0x8>;
brcm,int-map-mask = <0x44>, <0xf000000>;
brcm,int-map-mask = <0x44>, <0xf000000>, <0x100000>;
brcm,int-fwd-mask = <0x70000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <18>, <19>;
interrupt-names = "upg_main", "upg_bsc";
interrupts = <18>, <19>, <20>;
interrupt-names = "upg_main", "upg_bsc", "upg_spi";
};
sun_top_ctrl: syscon@404000 {
@ -226,5 +226,48 @@
interrupts = <61>;
status = "disabled";
};
spi_l2_intc: interrupt-controller@411d00 {
compatible = "brcm,l2-intc";
reg = <0x411d00 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <79>;
};
qspi: spi@443000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-qspi";
clocks = <&upg_clk>;
reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
reg-names = "cs_reg", "hif_mspi", "bspi";
interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
interrupt-parent = <&spi_l2_intc>;
interrupt-names = "spi_lr_fullness_reached",
"spi_lr_session_aborted",
"spi_lr_impatient",
"spi_lr_session_done",
"spi_lr_overread",
"mspi_done",
"mspi_halted";
status = "disabled";
};
mspi: spi@406400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-mspi";
clocks = <&upg_clk>;
reg = <0x406400 0x180>;
reg-names = "mspi";
interrupts = <0x14>;
interrupt-parent = <&upg_irq0_intc>;
interrupt-names = "mspi_done";
status = "disabled";
};
};
};

43
arch/mips/boot/dts/brcm/bcm7346.dtsi
View File

@ -439,5 +439,48 @@
interrupts = <85>;
status = "disabled";
};
spi_l2_intc: interrupt-controller@411d00 {
compatible = "brcm,l2-intc";
reg = <0x411d00 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <31>;
};
qspi: spi@413000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-qspi";
clocks = <&upg_clk>;
reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
reg-names = "cs_reg", "hif_mspi", "bspi";
interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
interrupt-parent = <&spi_l2_intc>;
interrupt-names = "spi_lr_fullness_reached",
"spi_lr_session_aborted",
"spi_lr_impatient",
"spi_lr_session_done",
"spi_lr_overread",
"mspi_done",
"mspi_halted";
status = "disabled";
};
mspi: spi@408a00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-mspi";
clocks = <&upg_clk>;
reg = <0x408a00 0x180>;
reg-names = "mspi";
interrupts = <0x14>;
interrupt-parent = <&upg_aon_irq0_intc>;
interrupt-names = "mspi_done";
status = "disabled";
};
};
};

43
arch/mips/boot/dts/brcm/bcm7358.dtsi
View File

@ -318,5 +318,48 @@
interrupts = <24>;
status = "disabled";
};
spi_l2_intc: interrupt-controller@411d00 {
compatible = "brcm,l2-intc";
reg = <0x411d00 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <31>;
};
qspi: spi@413000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-qspi";
clocks = <&upg_clk>;
reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
reg-names = "cs_reg", "hif_mspi", "bspi";
interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
interrupt-parent = <&spi_l2_intc>;
interrupt-names = "spi_lr_fullness_reached",
"spi_lr_session_aborted",
"spi_lr_impatient",
"spi_lr_session_done",
"spi_lr_overread",
"mspi_done",
"mspi_halted";
status = "disabled";
};
mspi: spi@408a00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-mspi";
clocks = <&upg_clk>;
reg = <0x408a00 0x180>;
reg-names = "mspi";
interrupts = <0x14>;
interrupt-parent = <&upg_aon_irq0_intc>;
interrupt-names = "mspi_done";
status = "disabled";
};
};
};

43
arch/mips/boot/dts/brcm/bcm7360.dtsi
View File

@ -358,5 +358,48 @@
interrupts = <82>;
status = "disabled";
};
spi_l2_intc: interrupt-controller@411d00 {
compatible = "brcm,l2-intc";
reg = <0x411d00 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <31>;
};
qspi: spi@413000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-qspi";
clocks = <&upg_clk>;
reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
reg-names = "cs_reg", "hif_mspi", "bspi";
interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
interrupt-parent = <&spi_l2_intc>;
interrupt-names = "spi_lr_fullness_reached",
"spi_lr_session_aborted",
"spi_lr_impatient",
"spi_lr_session_done",
"spi_lr_overread",
"mspi_done",
"mspi_halted";
status = "disabled";
};
mspi: spi@408a00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-mspi";
clocks = <&upg_clk>;
reg = <0x408a00 0x180>;
reg-names = "mspi";
interrupts = <0x14>;
interrupt-parent = <&upg_aon_irq0_intc>;
interrupt-names = "mspi_done";
status = "disabled";
};
};
};

43
arch/mips/boot/dts/brcm/bcm7362.dtsi
View File

@ -354,5 +354,48 @@
interrupts = <82>;
status = "disabled";
};
spi_l2_intc: interrupt-controller@411d00 {
compatible = "brcm,l2-intc";
reg = <0x411d00 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <31>;
};
qspi: spi@413000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-qspi";
clocks = <&upg_clk>;
reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
reg-names = "cs_reg", "hif_mspi", "bspi";
interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
interrupt-parent = <&spi_l2_intc>;
interrupt-names = "spi_lr_fullness_reached",
"spi_lr_session_aborted",
"spi_lr_impatient",
"spi_lr_session_done",
"spi_lr_overread",
"mspi_done",
"mspi_halted";
status = "disabled";
};
mspi: spi@408a00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-mspi";
clocks = <&upg_clk>;
reg = <0x408a00 0x180>;
reg-names = "mspi";
interrupts = <0x14>;
interrupt-parent = <&upg_aon_irq0_intc>;
interrupt-names = "mspi_done";
status = "disabled";
};
};
};

49
arch/mips/boot/dts/brcm/bcm7420.dtsi
View File

@ -92,15 +92,15 @@
compatible = "brcm,bcm7120-l2-intc";
reg = <0x406780 0x8>;
brcm,int-map-mask = <0x44>, <0x1f000000>;
brcm,int-map-mask = <0x44>, <0x1f000000>, <0x100000>;
brcm,int-fwd-mask = <0x70000>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <18>, <19>;
interrupt-names = "upg_main", "upg_bsc";
interrupts = <18>, <19>, <20>;
interrupt-names = "upg_main", "upg_bsc", "upg_spi";
};
sun_top_ctrl: syscon@404000 {
@ -287,5 +287,48 @@
interrupts = <62>;
status = "disabled";
};
spi_l2_intc: interrupt-controller@411d00 {
compatible = "brcm,l2-intc";
reg = <0x411d00 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <78>;
};
qspi: spi@443000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-qspi";
clocks = <&upg_clk>;
reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
reg-names = "cs_reg", "hif_mspi", "bspi";
interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
interrupt-parent = <&spi_l2_intc>;
interrupt-names = "spi_lr_fullness_reached",
"spi_lr_session_aborted",
"spi_lr_impatient",
"spi_lr_session_done",
"spi_lr_overread",
"mspi_done",
"mspi_halted";
status = "disabled";
};
mspi: spi@406400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-mspi";
clocks = <&upg_clk>;
reg = <0x406400 0x180>;
reg-names = "mspi";
interrupts = <0x14>;
interrupt-parent = <&upg_irq0_intc>;
interrupt-names = "mspi_done";
status = "disabled";
};
};
};

43
arch/mips/boot/dts/brcm/bcm7425.dtsi
View File

@ -450,5 +450,48 @@
mmc-hs200-1_8v;
status = "disabled";
};
spi_l2_intc: interrupt-controller@41ad00 {
compatible = "brcm,l2-intc";
reg = <0x41ad00 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <25>;
};
qspi: spi@41c000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-qspi";
clocks = <&upg_clk>;
reg = <0x419920 0x4 0x41c200 0x188 0x41c000 0x50>;
reg-names = "cs_reg", "hif_mspi", "bspi";
interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
interrupt-parent = <&spi_l2_intc>;
interrupt-names = "spi_lr_fullness_reached",
"spi_lr_session_aborted",
"spi_lr_impatient",
"spi_lr_session_done",
"spi_lr_overread",
"mspi_done",
"mspi_halted";
status = "disabled";
};
mspi: spi@409200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-mspi";
clocks = <&upg_clk>;
reg = <0x409200 0x180>;
reg-names = "mspi";
interrupts = <0x14>;
interrupt-parent = <&upg_aon_irq0_intc>;
interrupt-names = "mspi_done";
status = "disabled";
};
};
};

43
arch/mips/boot/dts/brcm/bcm7435.dtsi
View File

@ -465,5 +465,48 @@
mmc-hs200-1_8v;
status = "disabled";
};
spi_l2_intc: interrupt-controller@41bd00 {
compatible = "brcm,l2-intc";
reg = <0x41bd00 0x30>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&periph_intc>;
interrupts = <25>;
};
qspi: spi@41d200 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-qspi";
clocks = <&upg_clk>;
reg = <0x41a920 0x4 0x41d400 0x188 0x41d200 0x50>;
reg-names = "cs_reg", "hif_mspi", "bspi";
interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
interrupt-parent = <&spi_l2_intc>;
interrupt-names = "spi_lr_fullness_reached",
"spi_lr_session_aborted",
"spi_lr_impatient",
"spi_lr_session_done",
"spi_lr_overread",
"mspi_done",
"mspi_halted";
status = "disabled";
};
mspi: spi@409200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,spi-bcm-qspi",
"brcm,spi-brcmstb-mspi";
clocks = <&upg_clk>;
reg = <0x409200 0x180>;
reg-names = "mspi";
interrupts = <0x14>;
interrupt-parent = <&upg_aon_irq0_intc>;
interrupt-names = "mspi_done";
status = "disabled";
};
};
};

4
arch/mips/boot/dts/brcm/bcm97125cbmb.dts
View File

@ -57,3 +57,7 @@
&ohci0 {
status = "disabled";
};
&mspi {
status = "okay";
};

4
arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
View File

@ -109,3 +109,7 @@
&sdhci0 {
status = "okay";
};
&mspi {
status = "okay";
};

36
arch/mips/boot/dts/brcm/bcm97358svmb.dts
View File

@ -69,3 +69,39 @@
&nand {
status = "okay";
};
&qspi {
status = "okay";
m25p80@0 {
compatible = "m25p80";
reg = <0>;
spi-max-frequency = <40000000>;
spi-cpol;
spi-cpha;
use-bspi;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
flash0.cfe@0 {
reg = <0x0 0x200000>;
};
flash0.mac@200000 {
reg = <0x200000 0x40000>;
};
flash0.nvram@240000 {
reg = <0x240000 0x10000>;
};
};
};
};
&mspi {
status = "okay";
};

36
arch/mips/boot/dts/brcm/bcm97360svmb.dts
View File

@ -72,3 +72,39 @@
&sdhci0 {
status = "okay";
};
&qspi {
status = "okay";
m25p80@0 {
compatible = "m25p80";
reg = <0>;
spi-max-frequency = <40000000>;
spi-cpol;
spi-cpha;
use-bspi;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
flash0.cfe@0 {
reg = <0x0 0x200000>;
};
flash0.mac@200000 {
reg = <0x200000 0x40000>;
};
flash0.nvram@240000 {
reg = <0x240000 0x10000>;
};
};
};
};
&mspi {
status = "okay";
};

4
arch/mips/boot/dts/brcm/bcm97362svmb.dts
View File

@ -73,3 +73,7 @@
&sdhci0 {
status = "okay";
};
&mspi {
status = "okay";
};

4
arch/mips/boot/dts/brcm/bcm97420c.dts
View File

@ -79,3 +79,7 @@
&ohci1 {
status = "okay";
};
&mspi {
status = "okay";
};

36
arch/mips/boot/dts/brcm/bcm97425svmb.dts
View File

@ -107,3 +107,39 @@
&sdhci1 {
status = "okay";
};
&qspi {
status = "okay";
m25p80@0 {
compatible = "m25p80";
reg = <0>;
spi-max-frequency = <40000000>;
spi-cpol;
spi-cpha;
use-bspi;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
flash0.cfe@0 {
reg = <0x0 0x200000>;
};
flash0.mac@200000 {
reg = <0x200000 0x40000>;
};
flash0.nvram@240000 {
reg = <0x240000 0x10000>;
};
};
};
};
&mspi {
status = "okay";
};

4
arch/mips/boot/dts/brcm/bcm97435svmb.dts
View File

@ -115,3 +115,7 @@
&sdhci1 {
status = "okay";
};
&mspi {
status = "okay";
};

9
arch/mips/boot/dts/img/Makefile Normal file
View File

@ -0,0 +1,9 @@
dtb-$(CONFIG_MACH_PISTACHIO) += pistachio_marduk.dtb
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
# Force kbuild to make empty built-in.o if necessary
obj- += dummy.o
always := $(dtb-y)
clean-files := *.dtb *.dtb.S

924
arch/mips/boot/dts/img/pistachio.dtsi Normal file
View File

@ -0,0 +1,924 @@
/*
* Copyright (C) 2015, 2016 Imagination Technologies Ltd.
* Copyright (C) 2015 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/clock/pistachio-clk.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/reset/pistachio-resets.h>
/ {
compatible = "img,pistachio";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "mti,interaptiv";
reg = <0>;
clocks = <&clk_core CLK_MIPS_PLL>;
clock-names = "cpu";
clock-latency = <1000>;
operating-points = <
/* kHz uV(dummy) */
546000 1150000
520000 1100000
494000 1000000
468000 950000
442000 900000
416000 800000
>;
};
};
i2c0: i2c@18100000 {
compatible = "img,scb-i2c";
reg = <0x18100000 0x200>;
interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_periph PERIPH_CLK_I2C0>,
<&cr_periph SYS_CLK_I2C0>;
clock-names = "scb", "sys";
assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
<&clk_periph PERIPH_CLK_I2C0_DIV>;
assigned-clock-rates = <100000000>, <33333334>;
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@18100200 {
compatible = "img,scb-i2c";
reg = <0x18100200 0x200>;
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_periph PERIPH_CLK_I2C1>,
<&cr_periph SYS_CLK_I2C1>;
clock-names = "scb", "sys";
assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
<&clk_periph PERIPH_CLK_I2C1_DIV>;
assigned-clock-rates = <100000000>, <33333334>;
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@18100400 {
compatible = "img,scb-i2c";
reg = <0x18100400 0x200>;
interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_periph PERIPH_CLK_I2C2>,
<&cr_periph SYS_CLK_I2C2>;
clock-names = "scb", "sys";
assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
<&clk_periph PERIPH_CLK_I2C2_DIV>;
assigned-clock-rates = <100000000>, <33333334>;
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c3: i2c@18100600 {
compatible = "img,scb-i2c";
reg = <0x18100600 0x200>;
interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_periph PERIPH_CLK_I2C3>,
<&cr_periph SYS_CLK_I2C3>;
clock-names = "scb", "sys";
assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
<&clk_periph PERIPH_CLK_I2C3_DIV>;
assigned-clock-rates = <100000000>, <33333334>;
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
#address-cells = <1>;
#size-cells = <0>;
};
i2s_in: i2s-in@18100800 {
compatible = "img,i2s-in";
reg = <0x18100800 0x200>;
interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdc 30 0xffffffff 0>;
dma-names = "rx";
clocks = <&cr_periph SYS_CLK_I2S_IN>;
clock-names = "sys";
img,i2s-channels = <6>;
pinctrl-names = "default";
pinctrl-0 = <&i2s_in_pins>;
status = "disabled";
#sound-dai-cells = <0>;
};
i2s_out: i2s-out@18100a00 {
compatible = "img,i2s-out";
reg = <0x18100a00 0x200>;
interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdc 23 0xffffffff 0>;
dma-names = "tx";
clocks = <&cr_periph SYS_CLK_I2S_OUT>,
<&clk_core CLK_I2S>;
clock-names = "sys", "ref";
assigned-clocks = <&clk_core CLK_I2S_DIV>;
assigned-clock-rates = <12288000>;
img,i2s-channels = <6>;
pinctrl-names = "default";
pinctrl-0 = <&i2s_out_pins>;
status = "disabled";
resets = <&pistachio_reset PISTACHIO_RESET_I2S_OUT>;
reset-names = "rst";
#sound-dai-cells = <0>;
};
parallel_out: parallel-audio-out@18100c00 {
compatible = "img,parallel-out";
reg = <0x18100c00 0x100>;
interrupts = <GIC_SHARED 19 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdc 16 0xffffffff 0>;
dma-names = "tx";
clocks = <&cr_periph SYS_CLK_PAUD_OUT>,
<&clk_core CLK_AUDIO_DAC>;
clock-names = "sys", "ref";
assigned-clocks = <&clk_core CLK_AUDIO_DAC_DIV>;
assigned-clock-rates = <12288000>;
status = "disabled";
resets = <&pistachio_reset PISTACHIO_RESET_PRL_OUT>;
reset-names = "rst";
#sound-dai-cells = <0>;
};
spdif_out: spdif-out@18100d00 {
compatible = "img,spdif-out";
reg = <0x18100d00 0x100>;
interrupts = <GIC_SHARED 21 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdc 14 0xffffffff 0>;
dma-names = "tx";
clocks = <&cr_periph SYS_CLK_SPDIF_OUT>,
<&clk_core CLK_SPDIF>;
clock-names = "sys", "ref";
assigned-clocks = <&clk_core CLK_SPDIF_DIV>;
assigned-clock-rates = <12288000>;
pinctrl-names = "default";
pinctrl-0 = <&spdif_out_pin>;
status = "disabled";
resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>;
reset-names = "rst";
#sound-dai-cells = <0>;
};
spdif_in: spdif-in@18100e00 {
compatible = "img,spdif-in";
reg = <0x18100e00 0x100>;
interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdc 15 0xffffffff 0>;
dma-names = "rx";
clocks = <&cr_periph SYS_CLK_SPDIF_IN>;
clock-names = "sys";
pinctrl-names = "default";
pinctrl-0 = <&spdif_in_pin>;
status = "disabled";
#sound-dai-cells = <0>;
};
internal_dac: internal-dac {
compatible = "img,pistachio-internal-dac";
img,cr-top = <&cr_top>;
img,voltage-select = <1>;
#sound-dai-cells = <0>;
};
spfi0: spi@18100f00 {
compatible = "img,spfi";
reg = <0x18100f00 0x100>;
interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_core CLK_SPI0>, <&cr_periph SYS_CLK_SPI0_MASTER>;
clock-names = "sys", "spfi";
dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
dma-names = "rx", "tx";
spfi-max-frequency = <50000000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spfi1: spi@18101000 {
compatible = "img,spfi";
reg = <0x18101000 0x100>;
interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_core CLK_SPI1>, <&cr_periph SYS_CLK_SPI1>;
clock-names = "sys", "spfi";
dmas = <&mdc 1 0xffffffff 0>, <&mdc 2 0xffffffff 0>;
dma-names = "rx", "tx";
img,supports-quad-mode;
spfi-max-frequency = <50000000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
pwm: pwm@18101300 {
compatible = "img,pistachio-pwm";
reg = <0x18101300 0x100>;
clocks = <&clk_periph PERIPH_CLK_PWM>,
<&cr_periph SYS_CLK_PWM>;
clock-names = "pwm", "sys";
img,cr-periph = <&cr_periph>;
#pwm-cells = <2>;
status = "disabled";
};
uart0: uart@18101400 {
compatible = "snps,dw-apb-uart";
reg = <0x18101400 0x100>;
interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>;
clock-names = "baudclk", "apb_pclk";
assigned-clocks = <&clk_core CLK_UART0_INTERNAL_DIV>,
<&clk_core CLK_UART0_DIV>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-0 = <&uart0_pins>, <&uart0_rts_cts_pins>;
pinctrl-names = "default";
status = "disabled";
};
uart1: uart@18101500 {
compatible = "snps,dw-apb-uart";
reg = <0x18101500 0x100>;
interrupts = <GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_core CLK_UART1>, <&cr_periph SYS_CLK_UART1>;
clock-names = "baudclk", "apb_pclk";
assigned-clocks = <&clk_core CLK_UART1_INTERNAL_DIV>,
<&clk_core CLK_UART1_DIV>;
assigned-clock-rates = <114278400>, <1843200>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";
status = "disabled";
};
adc: adc@18101600 {
compatible = "cosmic,10001-adc";
reg = <0x18101600 0x24>;
adc-reserved-channels = <0x30>;
clocks = <&clk_core CLK_AUX_ADC>;
clock-names = "adc";
assigned-clocks = <&clk_core CLK_AUX_ADC_INTERNAL_DIV>,
<&clk_core CLK_AUX_ADC_DIV>;
assigned-clock-rates = <100000000>, <1000000>;
status = "disabled";
#io-channel-cells = <1>;
};
pinctrl: pinctrl@18101c00 {
compatible = "img,pistachio-system-pinctrl";
reg = <0x18101c00 0x400>;
gpio0: gpio0 {
interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 16>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio1 {
interrupts = <GIC_SHARED 72 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 16 16>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio2 {
interrupts = <GIC_SHARED 73 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 32 16>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio3 {
interrupts = <GIC_SHARED 74 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 48 16>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio4 {
interrupts = <GIC_SHARED 75 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 64 16>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio5 {
interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 80 10>;
interrupt-controller;
#interrupt-cells = <2>;
};
i2c0_pins: i2c0-pins {
pin_i2c0: i2c0 {
pins = "mfio28", "mfio29";
function = "i2c0";
drive-strength = <4>;
};
};
i2c1_pins: i2c1-pins {
pin_i2c1: i2c1 {
pins = "mfio30", "mfio31";
function = "i2c1";
drive-strength = <4>;
};
};
i2c2_pins: i2c2-pins {
pin_i2c2: i2c2 {
pins = "mfio32", "mfio33";
function = "i2c2";
drive-strength = <4>;
};
};
i2c3_pins: i2c3-pins {
pin_i2c3: i2c3 {
pins = "mfio34", "mfio35";
function = "i2c3";
drive-strength = <4>;
};
};
spim0_pins: spim0-pins {
pin_spim0: spim0 {
pins = "mfio9", "mfio10";
function = "spim0";
drive-strength = <4>;
};
spim0_clk: spim0-clk {
pins = "mfio8";
function = "spim0";
drive-strength = <4>;
};
};
spim0_cs0_alt_pin: spim0-cs0-alt-pin {
spim0-cs0 {
pins = "mfio2";
drive-strength = <2>;
};
};
spim0_cs1_pin: spim0-cs1-pin {
spim0-cs1 {
pins = "mfio1";
drive-strength = <2>;
};
};
spim0_cs2_pin: spim0-cs2-pin {
spim0-cs2 {
pins = "mfio55";
drive-strength = <2>;
};
};
spim0_cs2_alt_pin: spim0-cs2-alt-pin {
spim0-cs2 {
pins = "mfio28";
drive-strength = <2>;
};
};
spim0_cs3_pin: spim0-cs3-pin {
spim0-cs3 {
pins = "mfio56";
drive-strength = <2>;
};
};
spim0_cs3_alt_pin: spim0-cs3-alt-pin {
spim0-cs3 {
pins = "mfio29";
drive-strength = <2>;
};
};
spim0_cs4_pin: spim0-cs4-pin {
spim0-cs4 {
pins = "mfio57";
drive-strength = <2>;
};
};
spim0_cs4_alt_pin: spim0-cs4-alt-pin {
spim0-cs4 {
pins = "mfio30";
drive-strength = <2>;
};
};
spim1_pins: spim1-pins {
spim1 {
pins = "mfio3", "mfio4", "mfio5";
function = "spim1";
drive-strength = <2>;
};
};
spim1_quad_pins: spim1-quad-pins {
spim1-quad {
pins = "mfio6", "mfio7";
function = "spim1";
drive-strength = <2>;
};
};
spim1_cs0_pin: spim1-cs0-pins {
spim1-cs0 {
pins = "mfio0";
function = "spim1";
drive-strength = <2>;
};
};
spim1_cs1_pin: spim1-cs1-pin {
spim1-cs1 {
pins = "mfio1";
function = "spim1";
drive-strength = <2>;
};
};
spim1_cs1_alt_pin: spim1-cs1-alt-pin {
spim1-cs1 {
pins = "mfio58";
function = "spim1";
drive-strength = <2>;
};
};
spim1_cs2_pin: spim1-cs2-pin {
spim1-cs2 {
pins = "mfio2";
function = "spim1";
drive-strength = <2>;
};
};
spim1_cs2_alt0_pin: spim1-cs2-alt0-pin {
spim1-cs2 {
pins = "mfio31";
function = "spim1";
drive-strength = <2>;
};
};
spim1_cs2_alt1_pin: spim1-cs2-alt1-pin {
spim1-cs2 {
pins = "mfio55";
function = "spim1";
drive-strength = <2>;
};
};
spim1_cs3_pin: spim1-cs3-pin {
spim1-cs3 {
pins = "mfio56";
function = "spim1";
drive-strength = <2>;
};
};
spim1_cs4_pin: spim1-cs4-pin {
spim1-cs4 {
pins = "mfio57";
function = "spim1";
drive-strength = <2>;
};
};
uart0_pins: uart0-pins {
uart0 {
pins = "mfio55", "mfio56";
function = "uart0";
drive-strength = <2>;
};
};
uart0_rts_cts_pins: uart0-rts-cts-pins {
uart0-rts-cts {
pins = "mfio57", "mfio58";
function = "uart0";
drive-strength = <2>;
};
};
uart1_pins: uart1-pins {
uart1 {
pins = "mfio59", "mfio60";
function = "uart1";
drive-strength = <2>;
};
};
uart1_rts_cts_pins: uart1-rts-cts-pins {
uart1-rts-cts {
pins = "mfio1", "mfio2";
function = "uart1";
drive-strength = <2>;
};
};
enet_pins: enet-pins {
pin_enet: enet {
pins = "mfio63", "mfio64", "mfio65", "mfio66",
"mfio67", "mfio68", "mfio69", "mfio70";
function = "eth";
slew-rate = <1>;
drive-strength = <4>;
};
pin_enet_phy_clk: enet-phy-clk {
pins = "mfio71";
function = "eth";
slew-rate = <1>;
drive-strength = <8>;
};
};
sdhost_pins: sdhost-pins {
pin_sdhost_clk: sdhost-clk {
pins = "mfio15";
function = "sdhost";
slew-rate = <1>;
drive-strength = <4>;
};
pin_sdhost_cmd: sdhost-cmd {
pins = "mfio16";
function = "sdhost";
slew-rate = <1>;
drive-strength = <4>;
};
pin_sdhost_data: sdhost-data {
pins = "mfio17", "mfio18", "mfio19", "mfio20",
"mfio21", "mfio22", "mfio23", "mfio24";
function = "sdhost";
slew-rate = <1>;
drive-strength = <4>;
};
pin_sdhost_power_select: sdhost-power-select {
pins = "mfio25";
function = "sdhost";
slew-rate = <1>;
drive-strength = <2>;
};
pin_sdhost_card_detect: sdhost-card-detect {
pins = "mfio26";
function = "sdhost";
drive-strength = <2>;
};
pin_sdhost_write_protect: sdhost-write-protect {
pins = "mfio27";
function = "sdhost";
drive-strength = <2>;
};
};
ir_pin: ir-pin {
ir-data {
pins = "mfio72";
function = "ir";
drive-strength = <2>;
};
};
pwmpdm0_pin: pwmpdm0-pin {
pwmpdm0 {
pins = "mfio73";
function = "pwmpdm";
drive-strength = <2>;
};
};
pwmpdm1_pin: pwmpdm1-pin {
pwmpdm1 {
pins = "mfio74";
function = "pwmpdm";
drive-strength = <2>;
};
};
pwmpdm2_pin: pwmpdm2-pin {
pwmpdm2 {
pins = "mfio75";
function = "pwmpdm";
drive-strength = <2>;
};
};
pwmpdm3_pin: pwmpdm3-pin {
pwmpdm3 {
pins = "mfio76";
function = "pwmpdm";
drive-strength = <2>;
};
};
dac_clk_pin: dac-clk-pin {
pin_dac_clk: dac-clk {
pins = "mfio45";
function = "i2s_dac_clk";
drive-strength = <4>;
};
};
i2s_mclk_pin: i2s-mclk-pin {
pin_i2s_mclk: i2s-mclk {
pins = "mfio36";
function = "i2s_out";
drive-strength = <4>;
};
};
spdif_out_pin: spdif-out-pin {
spdif-out {
pins = "mfio61";
function = "spdif_out";
slew-rate = <1>;
drive-strength = <2>;
};
};
spdif_in_pin: spdif-in-pin {
spdif-in {
pins = "mfio62";
function = "spdif_in";
drive-strength = <2>;
};
};
i2s_out_pins: i2s-out-pins {
pins_i2s_out_clk: i2s-out-clk {
pins = "mfio37", "mfio38";
function = "i2s_out";
drive-strength = <4>;
};
pins_i2s_out: i2s-out {
pins = "mfio39", "mfio40",
"mfio41", "mfio42",
"mfio43", "mfio44";
function = "i2s_out";
drive-strength = <2>;
};
};
i2s_in_pins: i2s-in-pins {
i2s-in {
pins = "mfio47", "mfio48", "mfio49",
"mfio50", "mfio51", "mfio52",
"mfio53", "mfio54";
function = "i2s_in";
drive-strength = <2>;
};
};
};
timer: timer@18102000 {
compatible = "img,pistachio-gptimer";
reg = <0x18102000 0x100>;
interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>,
<&cr_periph SYS_CLK_TIMER>;
clock-names = "fast", "sys";
img,cr-periph = <&cr_periph>;
};
wdt: watchdog@18102100 {
compatible = "img,pdc-wdt";
reg = <0x18102100 0x100>;
interrupts = <GIC_SHARED 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_periph PERIPH_CLK_WD>, <&cr_periph SYS_CLK_WD>;
clock-names = "wdt", "sys";
assigned-clocks = <&clk_periph PERIPH_CLK_WD_PRE_DIV>,
<&clk_periph PERIPH_CLK_WD_DIV>;
assigned-clock-rates = <4000000>, <32768>;
};
ir: ir@18102200 {
compatible = "img,ir-rev1";
reg = <0x18102200 0x100>;
interrupts = <GIC_SHARED 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_periph PERIPH_CLK_IR>, <&cr_periph SYS_CLK_IR>;
clock-names = "core", "sys";
assigned-clocks = <&clk_periph PERIPH_CLK_IR_PRE_DIV>,
<&clk_periph PERIPH_CLK_IR_DIV>;
assigned-clock-rates = <4000000>, <32768>;
pinctrl-0 = <&ir_pin>;
pinctrl-names = "default";
status = "disabled";
};
usb: usb@18120000 {
compatible = "snps,dwc2";
reg = <0x18120000 0x1c000>;
interrupts = <GIC_SHARED 49 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb_phy>;
phy-names = "usb2-phy";
g-tx-fifo-size = <256 256 256 256>;
status = "disabled";
};
enet: ethernet@18140000 {
compatible = "snps,dwmac";
reg = <0x18140000 0x2000>;
interrupts = <GIC_SHARED 50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&clk_core CLK_ENET>, <&cr_periph SYS_CLK_ENET>;
clock-names = "stmmaceth", "pclk";
assigned-clocks = <&clk_core CLK_ENET_MUX>,
<&clk_core CLK_ENET_DIV>;
assigned-clock-parents = <&clk_core CLK_SYS_INTERNAL_DIV>;
assigned-clock-rates = <0>, <50000000>;
pinctrl-0 = <&enet_pins>;
pinctrl-names = "default";
phy-mode = "rmii";
status = "disabled";
};
sdhost: mmc@18142000 {
compatible = "img,pistachio-dw-mshc";
reg = <0x18142000 0x400>;
interrupts = <GIC_SHARED 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_core CLK_SD_HOST>, <&cr_periph SYS_CLK_SD_HOST>;
clock-names = "ciu", "biu";
pinctrl-0 = <&sdhost_pins>;
pinctrl-names = "default";
fifo-depth = <0x20>;
num-slots = <1>;
clock-frequency = <50000000>;
bus-width = <8>;
cap-mmc-highspeed;
cap-sd-highspeed;
status = "disabled";
};
sram: sram@1b000000 {
compatible = "mmio-sram";
reg = <0x1b000000 0x10000>;
};
mdc: dma-controller@18143000 {
compatible = "img,pistachio-mdc-dma";
reg = <0x18143000 0x1000>;
interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cr_periph SYS_CLK_MDC>;
clock-names = "sys";
img,max-burst-multiplier = <16>;
img,cr-periph = <&cr_periph>;
#dma-cells = <3>;
};
clk_core: clk@18144000 {
compatible = "img,pistachio-clk", "syscon";
clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
<&cr_top EXT_CLK_ENET_IN>;
clock-names = "xtal", "audio_refclk_ext_gate",
"ext_enet_in_gate";
reg = <0x18144000 0x800>;
#clock-cells = <1>;
};
clk_periph: clk@18144800 {
compatible = "img,pistachio-clk-periph";
reg = <0x18144800 0x1000>;
clocks = <&clk_core CLK_PERIPH_SYS>;
clock-names = "periph_sys_core";
#clock-cells = <1>;
};
cr_periph: clk@18148000 {
compatible = "img,pistachio-cr-periph", "syscon", "simple-bus";
reg = <0x18148000 0x1000>;
clocks = <&clk_periph PERIPH_CLK_SYS>;
clock-names = "sys";
#clock-cells = <1>;
pistachio_reset: reset-controller {
compatible = "img,pistachio-reset";
#reset-cells = <1>;
};
};
cr_top: clk@18149000 {
compatible = "img,pistachio-cr-top", "syscon";
reg = <0x18149000 0x200>;
#clock-cells = <1>;
};
hash: hash@18149600 {
compatible = "img,hash-accelerator";
reg = <0x18149600 0x100>, <0x18101100 0x4>;
interrupts = <GIC_SHARED 59 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&mdc 8 0xffffffff 0>;
dma-names = "tx";
clocks = <&cr_periph SYS_CLK_HASH>,
<&clk_periph PERIPH_CLK_ROM>;
clock-names = "sys", "hash";
};
gic: interrupt-controller@1bdc0000 {
compatible = "mti,gic";
reg = <0x1bdc0000 0x20000>;
interrupt-controller;
#interrupt-cells = <3>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clocks = <&clk_core CLK_MIPS>;
};
};
usb_phy: usb-phy {
compatible = "img,pistachio-usb-phy";
clocks = <&clk_core CLK_USB_PHY>;
clock-names = "usb_phy";
assigned-clocks = <&clk_core CLK_USB_PHY_DIV>;
assigned-clock-rates = <50000000>;
img,refclk = <0x2>;
img,cr-top = <&cr_top>;
#phy-cells = <0>;
};
xtal: xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <52000000>;
clock-output-names = "xtal";
};
};

163
arch/mips/boot/dts/img/pistachio_marduk.dts Normal file
View File

@ -0,0 +1,163 @@
/*
* Copyright (C) 2015, 2016 Imagination Technologies Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* IMG Marduk board is also known as Creator Ci40.
*/
/dts-v1/;
#include "pistachio.dtsi"
/ {
model = "IMG Marduk (Creator Ci40)";
compatible = "img,pistachio-marduk", "img,pistachio";
aliases {
serial0 = &uart0;
serial1 = &uart1;
ethernet0 = &enet;
spi0 = &spfi0;
spi1 = &spfi1;
};
chosen {
bootargs = "root=/dev/sda1 rootwait ro lpj=723968";
stdout-path = "serial1:115200";
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>;
};
reg_1v8: fixed-regulator {
compatible = "regulator-fixed";
regulator-name = "aux_adc_vref";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
internal_dac_supply: internal-dac-supply {
compatible = "regulator-fixed";
regulator-name = "internal_dac_supply";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
leds {
compatible = "pwm-leds";
heartbeat {
label = "marduk:red:heartbeat";
pwms = <&pwm 3 300000>;
max-brightness = <255>;
linux,default-trigger = "heartbeat";
};
};
keys {
compatible = "gpio-keys";
button@1 {
label = "Button 1";
linux,code = <0x101>; /* BTN_1 */
gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
};
button@2 {
label = "Button 2";
linux,code = <0x102>; /* BTN_2 */
gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
};
};
};
&internal_dac {
VDD-supply = <&internal_dac_supply>;
};
&spfi1 {
status = "okay";
pinctrl-0 = <&spim1_pins>, <&spim1_quad_pins>, <&spim1_cs0_pin>,
<&spim1_cs1_pin>;
pinctrl-names = "default";
cs-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>, <&gpio0 1 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "spansion,s25fl016k", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
};
};
&uart0 {
status = "okay";
assigned-clock-rates = <114278400>, <1843200>;
};
&uart1 {
status = "okay";
};
&usb {
status = "okay";
};
&enet {
status = "okay";
};
&pin_enet {
drive-strength = <2>;
};
&pin_enet_phy_clk {
drive-strength = <2>;
};
&sdhost {
status = "okay";
bus-width = <4>;
disable-wp;
};
&pin_sdhost_cmd {
drive-strength = <2>;
};
&pin_sdhost_data {
drive-strength = <2>;
};
&pwm {
status = "okay";
pinctrl-0 = <&pwmpdm0_pin>, <&pwmpdm1_pin>, <&pwmpdm2_pin>,
<&pwmpdm3_pin>;
pinctrl-names = "default";
};
&adc {
status = "okay";
vref-supply = <&reg_1v8>;
adc-reserved-channels = <0x10>;
};
&i2c2 {
status = "okay";
clock-frequency = <400000>;
tpm@20 {
compatible = "infineon,slb9645tt";
reg = <0x20>;
};
};
&i2c3 {
status = "okay";
clock-frequency = <400000>;
};

63
arch/mips/boot/dts/xilfpga/nexys4ddr.dts
View File

@ -17,6 +17,18 @@
compatible = "mti,cpu-interrupt-controller";
};
axi_intc: interrupt-controller@10200000 {
#interrupt-cells = <1>;
compatible = "xlnx,xps-intc-1.00.a";
interrupt-controller;
reg = <0x10200000 0x10000>;
xlnx,kind-of-intr = <0x0>;
xlnx,num-intr-inputs = <0x6>;
interrupt-parent = <&cpuintc>;
interrupts = <6>;
};
axi_gpio: gpio@10600000 {
#gpio-cells = <1>;
compatible = "xlnx,xps-gpio-1.00.a";
@ -30,6 +42,32 @@
xlnx,tri-default = <0xffffffff>;
} ;
axi_ethernetlite: ethernet@10e00000 {
compatible = "xlnx,xps-ethernetlite-3.00.a";
device_type = "network";
interrupt-parent = <&axi_intc>;
interrupts = <1>;
phy-handle = <&phy0>;
reg = <0x10e00000 0x10000>;
xlnx,duplex = <0x1>;
xlnx,include-global-buffers = <0x1>;
xlnx,include-internal-loopback = <0x0>;
xlnx,include-mdio = <0x1>;
xlnx,instance = "axi_ethernetlite_inst";
xlnx,rx-ping-pong = <0x1>;
xlnx,s-axi-id-width = <0x1>;
xlnx,tx-ping-pong = <0x1>;
xlnx,use-internal = <0x0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@1 {
device_type = "ethernet-phy";
reg = <1>;
};
};
};
axi_uart16550: serial@10400000 {
compatible = "ns16550a";
reg = <0x10400000 0x10000>;
@ -38,6 +76,31 @@
reg-offset = <0x1000>;
clocks = <&ext>;
interrupt-parent = <&axi_intc>;
interrupts = <0>;
};
axi_i2c: i2c@10A00000 {
compatible = "xlnx,xps-iic-2.00.a";
interrupt-parent = <&axi_intc>;
interrupts = <4>;
reg = < 0x10A00000 0x10000 >;
clocks = <&ext>;
xlnx,clk-freq = <0x5f5e100>;
xlnx,family = "Artix7";
xlnx,gpo-width = <0x1>;
xlnx,iic-freq = <0x186a0>;
xlnx,scl-inertial-delay = <0x0>;
xlnx,sda-inertial-delay = <0x0>;
xlnx,ten-bit-adr = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
ad7420@4B {
compatible = "adi,adt7420";
reg = <0x4B>;
};
} ;
};

1
arch/mips/cavium-octeon/Makefile
View File

@ -18,3 +18,4 @@ obj-y += crypto/
obj-$(CONFIG_MTD) += flash_setup.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o
obj-$(CONFIG_USB) += octeon-usb.o

2
arch/mips/cavium-octeon/crypto/octeon-crypto.c
View File

@ -7,7 +7,7 @@
*/
#include <asm/cop2.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/interrupt.h>
#include "octeon-crypto.h"

15
arch/mips/cavium-octeon/dma-octeon.c
View File

@ -164,19 +164,14 @@ static void *octeon_dma_alloc_coherent(struct device *dev, size_t size,
/* ignore region specifiers */
gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
#ifdef CONFIG_ZONE_DMA
if (dev == NULL)
if (IS_ENABLED(CONFIG_ZONE_DMA) && dev == NULL)
gfp |= __GFP_DMA;
else if (dev->coherent_dma_mask <= DMA_BIT_MASK(24))
else if (IS_ENABLED(CONFIG_ZONE_DMA) &&
dev->coherent_dma_mask <= DMA_BIT_MASK(24))
gfp |= __GFP_DMA;
else
#endif
#ifdef CONFIG_ZONE_DMA32
if (dev->coherent_dma_mask <= DMA_BIT_MASK(32))
else if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
dev->coherent_dma_mask <= DMA_BIT_MASK(32))
gfp |= __GFP_DMA32;
else
#endif
;
/* Don't invoke OOM killer */
gfp |= __GFP_NORETRY;

2
arch/mips/cavium-octeon/executive/cvmx-bootmem.c
View File

@ -30,8 +30,8 @@
* application start time.
*/
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/octeon/cvmx.h>
#include <asm/octeon/cvmx-spinlock.h>

2
arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
View File

@ -33,7 +33,7 @@
* these functions directly.
*
*/
#include <linux/module.h>
#include <linux/export.h>
#include <asm/octeon/octeon.h>

3
arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
View File

@ -287,8 +287,7 @@ cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port)
* Configure an IPD/PKO port for the specified link state. This
* function does not influence auto negotiation at the PHY level.
* The passed link state must always match the link state returned
* by cvmx_helper_link_get(). It is normally best to use
* cvmx_helper_link_autoconf() instead.
* by cvmx_helper_link_get().
*
* @ipd_port: IPD/PKO port to configure
* @link_info: The new link state

3
arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
View File

@ -500,8 +500,7 @@ cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port)
* Configure an IPD/PKO port for the specified link state. This
* function does not influence auto negotiation at the PHY level.
* The passed link state must always match the link state returned
* by cvmx_helper_link_get(). It is normally best to use
* cvmx_helper_link_autoconf() instead.
* by cvmx_helper_link_get().
*
* @ipd_port: IPD/PKO port to configure
* @link_info: The new link state

3
arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
View File

@ -188,8 +188,7 @@ cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port)
* Configure an IPD/PKO port for the specified link state. This
* function does not influence auto negotiation at the PHY level.
* The passed link state must always match the link state returned
* by cvmx_helper_link_get(). It is normally best to use
* cvmx_helper_link_autoconf() instead.
* by cvmx_helper_link_get().
*
* @ipd_port: IPD/PKO port to configure
* @link_info: The new link state

3
arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
View File

@ -295,8 +295,7 @@ cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port)
* Configure an IPD/PKO port for the specified link state. This
* function does not influence auto negotiation at the PHY level.
* The passed link state must always match the link state returned
* by cvmx_helper_link_get(). It is normally best to use
* cvmx_helper_link_autoconf() instead.
* by cvmx_helper_link_get().
*
* @ipd_port: IPD/PKO port to configure
* @link_info: The new link state

47
arch/mips/cavium-octeon/executive/cvmx-helper.c
View File

@ -69,10 +69,6 @@ void (*cvmx_override_ipd_port_setup) (int ipd_port);
/* Port count per interface */
static int interface_port_count[5];
/* Port last configured link info index by IPD/PKO port */
static cvmx_helper_link_info_t
port_link_info[CVMX_PIP_NUM_INPUT_PORTS];
/**
* Return the number of interfaces the chip has. Each interface
* may have multiple ports. Most chips support two interfaces,
@ -1135,41 +1131,6 @@ int cvmx_helper_initialize_packet_io_local(void)
return cvmx_pko_initialize_local();
}
/**
* Auto configure an IPD/PKO port link state and speed. This
* function basically does the equivalent of:
* cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port));
*
* @ipd_port: IPD/PKO port to auto configure
*
* Returns Link state after configure
*/
cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port)
{
cvmx_helper_link_info_t link_info;
int interface = cvmx_helper_get_interface_num(ipd_port);
int index = cvmx_helper_get_interface_index_num(ipd_port);
if (index >= cvmx_helper_ports_on_interface(interface)) {
link_info.u64 = 0;
return link_info;
}
link_info = cvmx_helper_link_get(ipd_port);
if (link_info.u64 == port_link_info[ipd_port].u64)
return link_info;
/* If we fail to set the link speed, port_link_info will not change */
cvmx_helper_link_set(ipd_port, link_info);
/*
* port_link_info should be the current value, which will be
* different than expect if cvmx_helper_link_set() failed.
*/
return port_link_info[ipd_port];
}
EXPORT_SYMBOL_GPL(cvmx_helper_link_autoconf);
/**
* Return the link state of an IPD/PKO port as returned by
* auto negotiation. The result of this function may not match
@ -1233,8 +1194,7 @@ EXPORT_SYMBOL_GPL(cvmx_helper_link_get);
* Configure an IPD/PKO port for the specified link state. This
* function does not influence auto negotiation at the PHY level.
* The passed link state must always match the link state returned
* by cvmx_helper_link_get(). It is normally best to use
* cvmx_helper_link_autoconf() instead.
* by cvmx_helper_link_get().
*
* @ipd_port: IPD/PKO port to configure
* @link_info: The new link state
@ -1276,11 +1236,6 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
case CVMX_HELPER_INTERFACE_MODE_LOOP:
break;
}
/* Set the port_link_info here so that the link status is updated
no matter how cvmx_helper_link_set is called. We don't change
the value if link_set failed */
if (result == 0)
port_link_info[ipd_port].u64 = link_info.u64;
return result;
}
EXPORT_SYMBOL_GPL(cvmx_helper_link_set);

2
arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
View File

@ -29,7 +29,7 @@
* This module provides system/board/application information obtained
* by the bootloader.
*/
#include <linux/module.h>
#include <linux/export.h>
#include <asm/octeon/cvmx.h>
#include <asm/octeon/cvmx-sysinfo.h>

25
arch/mips/cavium-octeon/octeon-memcpy.S
View File

@ -15,6 +15,7 @@
#include <asm/asm.h>
#include <asm/asm-offsets.h>
#include <asm/export.h>
#include <asm/regdef.h>
#define dst a0
@ -142,6 +143,7 @@
* t7 is used as a flag to note inatomic mode.
*/
LEAF(__copy_user_inatomic)
EXPORT_SYMBOL(__copy_user_inatomic)
b __copy_user_common
li t7, 1
END(__copy_user_inatomic)
@ -154,9 +156,11 @@ LEAF(__copy_user_inatomic)
*/
.align 5
LEAF(memcpy) /* a0=dst a1=src a2=len */
EXPORT_SYMBOL(memcpy)
move v0, dst /* return value */
__memcpy:
FEXPORT(__copy_user)
EXPORT_SYMBOL(__copy_user)
li t7, 0 /* not inatomic */
__copy_user_common:
/*
@ -208,18 +212,18 @@ EXC( STORE t2, UNIT(6)(dst), s_exc_p10u)
ADD src, src, 16*NBYTES
EXC( STORE t3, UNIT(7)(dst), s_exc_p9u)
ADD dst, dst, 16*NBYTES
EXC( LOAD t0, UNIT(-8)(src), l_exc_copy)
EXC( LOAD t1, UNIT(-7)(src), l_exc_copy)
EXC( LOAD t2, UNIT(-6)(src), l_exc_copy)
EXC( LOAD t3, UNIT(-5)(src), l_exc_copy)
EXC( LOAD t0, UNIT(-8)(src), l_exc_copy_rewind16)
EXC( LOAD t1, UNIT(-7)(src), l_exc_copy_rewind16)
EXC( LOAD t2, UNIT(-6)(src), l_exc_copy_rewind16)
EXC( LOAD t3, UNIT(-5)(src), l_exc_copy_rewind16)
EXC( STORE t0, UNIT(-8)(dst), s_exc_p8u)
EXC( STORE t1, UNIT(-7)(dst), s_exc_p7u)
EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u)
EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u)
EXC( LOAD t0, UNIT(-4)(src), l_exc_copy)
EXC( LOAD t1, UNIT(-3)(src), l_exc_copy)
EXC( LOAD t2, UNIT(-2)(src), l_exc_copy)
EXC( LOAD t3, UNIT(-1)(src), l_exc_copy)
EXC( LOAD t0, UNIT(-4)(src), l_exc_copy_rewind16)
EXC( LOAD t1, UNIT(-3)(src), l_exc_copy_rewind16)
EXC( LOAD t2, UNIT(-2)(src), l_exc_copy_rewind16)
EXC( LOAD t3, UNIT(-1)(src), l_exc_copy_rewind16)
EXC( STORE t0, UNIT(-4)(dst), s_exc_p4u)
EXC( STORE t1, UNIT(-3)(dst), s_exc_p3u)
EXC( STORE t2, UNIT(-2)(dst), s_exc_p2u)
@ -383,6 +387,10 @@ done:
nop
END(memcpy)
l_exc_copy_rewind16:
/* Rewind src and dst by 16*NBYTES for l_exc_copy */
SUB src, src, 16*NBYTES
SUB dst, dst, 16*NBYTES
l_exc_copy:
/*
* Copy bytes from src until faulting load address (or until a
@ -459,6 +467,7 @@ s_exc:
.align 5
LEAF(memmove)
EXPORT_SYMBOL(memmove)
ADD t0, a0, a2
ADD t1, a1, a2
sltu t0, a1, t0 # dst + len <= src -> memcpy

1
arch/mips/cavium-octeon/octeon-platform.c
View File

@ -448,6 +448,7 @@ static struct of_device_id __initdata octeon_ids[] = {
{ .compatible = "cavium,octeon-3860-bootbus", },
{ .compatible = "cavium,mdio-mux", },
{ .compatible = "gpio-leds", },
{ .compatible = "cavium,octeon-7130-usb-uctl", },
{},
};

552
arch/mips/cavium-octeon/octeon-usb.c Normal file
View File

@ -0,0 +1,552 @@
/*
* XHCI HCD glue for Cavium Octeon III SOCs.
*
* Copyright (C) 2010-2017 Cavium Networks
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/of_platform.h>
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-gpio-defs.h>
/* USB Control Register */
union cvm_usbdrd_uctl_ctl {
uint64_t u64;
struct cvm_usbdrd_uctl_ctl_s {
/* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */
__BITFIELD_FIELD(uint64_t clear_bist:1,
/* 1 = Start BIST and cleared by hardware */
__BITFIELD_FIELD(uint64_t start_bist:1,
/* Reference clock select for SuperSpeed and HighSpeed PLLs:
* 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
* 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
* 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
* HighSpeed PLL uses PLL_REF_CLK for reference clck
* 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
* HighSpeed PLL uses PLL_REF_CLK for reference clck
*/
__BITFIELD_FIELD(uint64_t ref_clk_sel:2,
/* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
__BITFIELD_FIELD(uint64_t ssc_en:1,
/* Spread-spectrum clock modulation range:
* 0x0 = -4980 ppm downspread
* 0x1 = -4492 ppm downspread
* 0x2 = -4003 ppm downspread
* 0x3 - 0x7 = Reserved
*/
__BITFIELD_FIELD(uint64_t ssc_range:3,
/* Enable non-standard oscillator frequencies:
* [55:53] = modules -1
* [52:47] = 2's complement push amount, 0 = Feature disabled
*/
__BITFIELD_FIELD(uint64_t ssc_ref_clk_sel:9,
/* Reference clock multiplier for non-standard frequencies:
* 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
* 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
* 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
* Other Values = Reserved
*/
__BITFIELD_FIELD(uint64_t mpll_multiplier:7,
/* Enable reference clock to prescaler for SuperSpeed functionality.
* Should always be set to "1"
*/
__BITFIELD_FIELD(uint64_t ref_ssp_en:1,
/* Divide the reference clock by 2 before entering the
* REF_CLK_FSEL divider:
* If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
* If REF_CLK_SEL = 0x2 or 0x3, then:
* 0x1 = DLMC_REF_CLK* is 125MHz
* 0x0 = DLMC_REF_CLK* is another supported frequency
*/
__BITFIELD_FIELD(uint64_t ref_clk_div2:1,
/* Select reference clock freqnuency for both PLL blocks:
* 0x27 = REF_CLK_SEL is 0x0 or 0x1
* 0x07 = REF_CLK_SEL is 0x2 or 0x3
*/
__BITFIELD_FIELD(uint64_t ref_clk_fsel:6,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_31_31:1,
/* Controller clock enable. */
__BITFIELD_FIELD(uint64_t h_clk_en:1,
/* Select bypass input to controller clock divider:
* 0x0 = Use divided coprocessor clock from H_CLKDIV
* 0x1 = Use clock from GPIO pins
*/
__BITFIELD_FIELD(uint64_t h_clk_byp_sel:1,
/* Reset controller clock divider. */
__BITFIELD_FIELD(uint64_t h_clkdiv_rst:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_27_27:1,
/* Clock divider select:
* 0x0 = divide by 1
* 0x1 = divide by 2
* 0x2 = divide by 4
* 0x3 = divide by 6
* 0x4 = divide by 8
* 0x5 = divide by 16
* 0x6 = divide by 24
* 0x7 = divide by 32
*/
__BITFIELD_FIELD(uint64_t h_clkdiv_sel:3,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_22_23:2,
/* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t usb3_port_perm_attach:1,
/* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t usb2_port_perm_attach:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_19_19:1,
/* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t usb3_port_disable:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_17_17:1,
/* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t usb2_port_disable:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_15_15:1,
/* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t ss_power_en:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_13_13:1,
/* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t hs_power_en:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_5_11:7,
/* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t csclk_en:1,
/* Controller mode: 0x0 = Host, 0x1 = Device */
__BITFIELD_FIELD(uint64_t drd_mode:1,
/* PHY reset */
__BITFIELD_FIELD(uint64_t uphy_rst:1,
/* Software reset UAHC */
__BITFIELD_FIELD(uint64_t uahc_rst:1,
/* Software resets UCTL */
__BITFIELD_FIELD(uint64_t uctl_rst:1,
;)))))))))))))))))))))))))))))))))
} s;
};
/* UAHC Configuration Register */
union cvm_usbdrd_uctl_host_cfg {
uint64_t u64;
struct cvm_usbdrd_uctl_host_cfg_s {
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_60_63:4,
/* Indicates minimum value of all received BELT values */
__BITFIELD_FIELD(uint64_t host_current_belt:12,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_38_47:10,
/* HS jitter adjustment */
__BITFIELD_FIELD(uint64_t fla:6,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_29_31:3,
/* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
__BITFIELD_FIELD(uint64_t bme:1,
/* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */
__BITFIELD_FIELD(uint64_t oci_en:1,
/* Overcurrent sene selection:
* 0x0 = Overcurrent indication from off-chip is active-low
* 0x1 = Overcurrent indication from off-chip is active-high
*/
__BITFIELD_FIELD(uint64_t oci_active_high_en:1,
/* Port power control enable: 0x0 = unavailable, 0x1 = available */
__BITFIELD_FIELD(uint64_t ppc_en:1,
/* Port power control sense selection:
* 0x0 = Port power to off-chip is active-low
* 0x1 = Port power to off-chip is active-high
*/
__BITFIELD_FIELD(uint64_t ppc_active_high_en:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_0_23:24,
;)))))))))))
} s;
};
/* UCTL Shim Features Register */
union cvm_usbdrd_uctl_shim_cfg {
uint64_t u64;
struct cvm_usbdrd_uctl_shim_cfg_s {
/* Out-of-bound UAHC register access: 0 = read, 1 = write */
__BITFIELD_FIELD(uint64_t xs_ncb_oob_wrn:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_60_62:3,
/* SRCID error log for out-of-bound UAHC register access:
* [59:58] = chipID
* [57] = Request source: 0 = core, 1 = NCB-device
* [56:51] = Core/NCB-device number, [56] always 0 for NCB devices
* [50:48] = SubID
*/
__BITFIELD_FIELD(uint64_t xs_ncb_oob_osrc:12,
/* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */
__BITFIELD_FIELD(uint64_t xm_bad_dma_wrn:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_44_46:3,
/* Encoded error type for bad UAHC DMA */
__BITFIELD_FIELD(uint64_t xm_bad_dma_type:4,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_13_39:27,
/* Select the IOI read command used by DMA accesses */
__BITFIELD_FIELD(uint64_t dma_read_cmd:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_10_11:2,
/* Select endian format for DMA accesses to the L2c:
* 0x0 = Little endian
*` 0x1 = Big endian
* 0x2 = Reserved
* 0x3 = Reserved
*/
__BITFIELD_FIELD(uint64_t dma_endian_mode:2,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_2_7:6,
/* Select endian format for IOI CSR access to UAHC:
* 0x0 = Little endian
*` 0x1 = Big endian
* 0x2 = Reserved
* 0x3 = Reserved
*/
__BITFIELD_FIELD(uint64_t csr_endian_mode:2,
;))))))))))))
} s;
};
#define OCTEON_H_CLKDIV_SEL 8
#define OCTEON_MIN_H_CLK_RATE 150000000
#define OCTEON_MAX_H_CLK_RATE 300000000
static DEFINE_MUTEX(dwc3_octeon_clocks_mutex);
static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
static int dwc3_octeon_config_power(struct device *dev, u64 base)
{
#define UCTL_HOST_CFG 0xe0
union cvm_usbdrd_uctl_host_cfg uctl_host_cfg;
union cvmx_gpio_bit_cfgx gpio_bit;
uint32_t gpio_pwr[3];
int gpio, len, power_active_low;
struct device_node *node = dev->of_node;
int index = (base >> 24) & 1;
if (of_find_property(node, "power", &len) != NULL) {
if (len == 12) {
of_property_read_u32_array(node, "power", gpio_pwr, 3);
power_active_low = gpio_pwr[2] & 0x01;
gpio = gpio_pwr[1];
} else if (len == 8) {
of_property_read_u32_array(node, "power", gpio_pwr, 2);
power_active_low = 0;
gpio = gpio_pwr[1];
} else {
dev_err(dev, "dwc3 controller clock init failure.\n");
return -EINVAL;
}
if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
OCTEON_IS_MODEL(OCTEON_CNF75XX))
&& gpio <= 31) {
gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
gpio_bit.s.tx_oe = 1;
gpio_bit.cn73xx.output_sel = (index == 0 ? 0x14 : 0x15);
cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
} else if (gpio <= 15) {
gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
gpio_bit.s.tx_oe = 1;
gpio_bit.cn70xx.output_sel = (index == 0 ? 0x14 : 0x19);
cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
} else {
gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio));
gpio_bit.s.tx_oe = 1;
gpio_bit.cn70xx.output_sel = (index == 0 ? 0x14 : 0x19);
cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64);
}
/* Enable XHCI power control and set if active high or low. */
uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
uctl_host_cfg.s.ppc_en = 1;
uctl_host_cfg.s.ppc_active_high_en = !power_active_low;
cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
} else {
/* Disable XHCI power control and set if active high. */
uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
uctl_host_cfg.s.ppc_en = 0;
uctl_host_cfg.s.ppc_active_high_en = 0;
cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
dev_warn(dev, "dwc3 controller clock init failure.\n");
}
return 0;
}
static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
{
union cvm_usbdrd_uctl_ctl uctl_ctl;
int ref_clk_sel = 2;
u64 div;
u32 clock_rate;
int mpll_mul;
int i;
u64 h_clk_rate;
u64 uctl_ctl_reg = base;
if (dev->of_node) {
const char *ss_clock_type;
const char *hs_clock_type;
i = of_property_read_u32(dev->of_node,
"refclk-frequency", &clock_rate);
if (i) {
pr_err("No UCTL \"refclk-frequency\"\n");
return -EINVAL;
}
i = of_property_read_string(dev->of_node,
"refclk-type-ss", &ss_clock_type);
if (i) {
pr_err("No UCTL \"refclk-type-ss\"\n");
return -EINVAL;
}
i = of_property_read_string(dev->of_node,
"refclk-type-hs", &hs_clock_type);
if (i) {
pr_err("No UCTL \"refclk-type-hs\"\n");
return -EINVAL;
}
if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0)
ref_clk_sel = 0;
else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
ref_clk_sel = 2;
else
pr_err("Invalid HS clock type %s, using pll_ref_clk instead\n",
hs_clock_type);
} else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0)
ref_clk_sel = 1;
else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
ref_clk_sel = 3;
else {
pr_err("Invalid HS clock type %s, using pll_ref_clk instead\n",
hs_clock_type);
ref_clk_sel = 3;
}
} else
pr_err("Invalid SS clock type %s, using dlmc_ref_clk0 instead\n",
ss_clock_type);
if ((ref_clk_sel == 0 || ref_clk_sel == 1) &&
(clock_rate != 100000000))
pr_err("Invalid UCTL clock rate of %u, using 100000000 instead\n",
clock_rate);
} else {
pr_err("No USB UCTL device node\n");
return -EINVAL;
}
/*
* Step 1: Wait for all voltages to be stable...that surely
* happened before starting the kernel. SKIP
*/
/* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */
/* Step 3: Assert all resets. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.uphy_rst = 1;
uctl_ctl.s.uahc_rst = 1;
uctl_ctl.s.uctl_rst = 1;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
/* Step 4a: Reset the clock dividers. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.h_clkdiv_rst = 1;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
/* Step 4b: Select controller clock frequency. */
for (div = 0; div < OCTEON_H_CLKDIV_SEL; div++) {
h_clk_rate = octeon_get_io_clock_rate() / clk_div[div];
if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE &&
h_clk_rate >= OCTEON_MIN_H_CLK_RATE)
break;
}
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.h_clkdiv_sel = div;
uctl_ctl.s.h_clk_en = 1;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
if ((div != uctl_ctl.s.h_clkdiv_sel) || (!uctl_ctl.s.h_clk_en)) {
dev_err(dev, "dwc3 controller clock init failure.\n");
return -EINVAL;
}
/* Step 4c: Deassert the controller clock divider reset. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.h_clkdiv_rst = 0;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
/* Step 5a: Reference clock configuration. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.ref_clk_sel = ref_clk_sel;
uctl_ctl.s.ref_clk_fsel = 0x07;
uctl_ctl.s.ref_clk_div2 = 0;
switch (clock_rate) {
default:
dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n",
clock_rate);
case 100000000:
mpll_mul = 0x19;
if (ref_clk_sel < 2)
uctl_ctl.s.ref_clk_fsel = 0x27;
break;
case 50000000:
mpll_mul = 0x32;
break;
case 125000000:
mpll_mul = 0x28;
break;
}
uctl_ctl.s.mpll_multiplier = mpll_mul;
/* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */
uctl_ctl.s.ssc_en = 1;
/* Step 5c: Enable SuperSpeed. */
uctl_ctl.s.ref_ssp_en = 1;
/* Step 5d: Cofngiure PHYs. SKIP */
/* Step 6a & 6b: Power up PHYs. */
uctl_ctl.s.hs_power_en = 1;
uctl_ctl.s.ss_power_en = 1;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
/* Step 7: Wait 10 controller-clock cycles to take effect. */
udelay(10);
/* Step 8a: Deassert UCTL reset signal. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.uctl_rst = 0;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
/* Step 8b: Wait 10 controller-clock cycles. */
udelay(10);
/* Steo 8c: Setup power-power control. */
if (dwc3_octeon_config_power(dev, base)) {
dev_err(dev, "Error configuring power.\n");
return -EINVAL;
}
/* Step 8d: Deassert UAHC reset signal. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.uahc_rst = 0;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
/* Step 8e: Wait 10 controller-clock cycles. */
udelay(10);
/* Step 9: Enable conditional coprocessor clock of UCTL. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.csclk_en = 1;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
/*Step 10: Set for host mode only. */
uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
uctl_ctl.s.drd_mode = 0;
cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
return 0;
}
static void __init dwc3_octeon_set_endian_mode(u64 base)
{
#define UCTL_SHIM_CFG 0xe8
union cvm_usbdrd_uctl_shim_cfg shim_cfg;
shim_cfg.u64 = cvmx_read_csr(base + UCTL_SHIM_CFG);
#ifdef __BIG_ENDIAN
shim_cfg.s.dma_endian_mode = 1;
shim_cfg.s.csr_endian_mode = 1;
#else
shim_cfg.s.dma_endian_mode = 0;
shim_cfg.s.csr_endian_mode = 0;
#endif
cvmx_write_csr(base + UCTL_SHIM_CFG, shim_cfg.u64);
}
#define CVMX_USBDRDX_UCTL_CTL(index) \
(CVMX_ADD_IO_SEG(0x0001180068000000ull) + \
((index & 1) * 0x1000000ull))
static void __init dwc3_octeon_phy_reset(u64 base)
{
union cvm_usbdrd_uctl_ctl uctl_ctl;
int index = (base >> 24) & 1;
uctl_ctl.u64 = cvmx_read_csr(CVMX_USBDRDX_UCTL_CTL(index));
uctl_ctl.s.uphy_rst = 0;
cvmx_write_csr(CVMX_USBDRDX_UCTL_CTL(index), uctl_ctl.u64);
}
static int __init dwc3_octeon_device_init(void)
{
const char compat_node_name[] = "cavium,octeon-7130-usb-uctl";
struct platform_device *pdev;
struct device_node *node;
struct resource *res;
void __iomem *base;
/*
* There should only be three universal controllers, "uctl"
* in the device tree. Two USB and a SATA, which we ignore.
*/
node = NULL;
do {
node = of_find_node_by_name(node, "uctl");
if (!node)
return -ENODEV;
if (of_device_is_compatible(node, compat_node_name)) {
pdev = of_find_device_by_node(node);
if (!pdev)
return -ENODEV;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
dev_err(&pdev->dev, "No memory resources\n");
return -ENXIO;
}
/*
* The code below maps in the registers necessary for
* setting up the clocks and reseting PHYs. We must
* release the resources so the dwc3 subsystem doesn't
* know the difference.
*/
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
mutex_lock(&dwc3_octeon_clocks_mutex);
dwc3_octeon_clocks_start(&pdev->dev, (u64)base);
dwc3_octeon_set_endian_mode((u64)base);
dwc3_octeon_phy_reset((u64)base);
dev_info(&pdev->dev, "clocks initialized.\n");
mutex_unlock(&dwc3_octeon_clocks_mutex);
devm_iounmap(&pdev->dev, base);
devm_release_mem_region(&pdev->dev, res->start,
resource_size(res));
}
} while (node != NULL);
return 0;
}
device_initcall(dwc3_octeon_device_init);
MODULE_AUTHOR("David Daney <david.daney@cavium.com>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("USB driver for OCTEON III SoC");

23
arch/mips/cavium-octeon/setup.c
View File

@ -949,6 +949,29 @@ static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
}
#endif /* CONFIG_CRASH_DUMP */
void __init fw_init_cmdline(void)
{
int i;
octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
for (i = 0; i < octeon_boot_desc_ptr->argc; i++) {
const char *arg =
cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
if (strlen(arcs_cmdline) + strlen(arg) + 1 <
sizeof(arcs_cmdline) - 1) {
strcat(arcs_cmdline, " ");
strcat(arcs_cmdline, arg);
}
}
}
void __init *plat_get_fdt(void)
{
octeon_bootinfo =
cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
return phys_to_virt(octeon_bootinfo->fdt_addr);
}
void __init plat_mem_setup(void)
{
uint64_t mem_alloc_size;

24
arch/mips/cavium-octeon/smp.c
View File

@ -11,7 +11,8 @@
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/export.h>
#include <asm/mmu_context.h>
#include <asm/time.h>
@ -24,12 +25,17 @@
volatile unsigned long octeon_processor_boot = 0xff;
volatile unsigned long octeon_processor_sp;
volatile unsigned long octeon_processor_gp;
#ifdef CONFIG_RELOCATABLE
volatile unsigned long octeon_processor_relocated_kernel_entry;
#endif /* CONFIG_RELOCATABLE */
#ifdef CONFIG_HOTPLUG_CPU
uint64_t octeon_bootloader_entry_addr;
EXPORT_SYMBOL(octeon_bootloader_entry_addr);
#endif
extern void kernel_entry(unsigned long arg1, ...);
static void octeon_icache_flush(void)
{
asm volatile ("synci 0($0)\n");
@ -180,6 +186,19 @@ static void __init octeon_smp_setup(void)
octeon_smp_hotplug_setup();
}
#ifdef CONFIG_RELOCATABLE
int plat_post_relocation(long offset)
{
unsigned long entry = (unsigned long)kernel_entry;
/* Send secondaries into relocated kernel */
octeon_processor_relocated_kernel_entry = entry + offset;
return 0;
}
#endif /* CONFIG_RELOCATABLE */
/**
* Firmware CPU startup hook
*
@ -272,7 +291,6 @@ static int octeon_cpu_disable(void)
set_cpu_online(cpu, false);
calculate_cpu_foreign_map();
cpumask_clear_cpu(cpu, &cpu_callin_map);
octeon_fixup_irqs();
__flush_cache_all();
@ -333,8 +351,6 @@ void play_dead(void)
;
}
extern void kernel_entry(unsigned long arg1, ...);
static void start_after_reset(void)
{
kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */

1
arch/mips/configs/cavium_octeon_defconfig
View File

@ -45,6 +45,7 @@ CONFIG_SYN_COOKIES=y
# CONFIG_INET_LRO is not set
CONFIG_IPV6=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
# CONFIG_MTD_OF_PARTS is not set

4
arch/mips/configs/ip22_defconfig
View File

@ -67,8 +67,8 @@ CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NF_CONNTRACK=m
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CT_PROTO_DCCP=m
CONFIG_NF_CT_PROTO_UDPLITE=m
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m

3
arch/mips/configs/ip27_defconfig
View File

@ -133,7 +133,7 @@ CONFIG_LIBFC=m
CONFIG_SCSI_QLOGIC_1280=y
CONFIG_SCSI_PMCRAID=m
CONFIG_SCSI_BFA_FC=m
CONFIG_SCSI_DH=m
CONFIG_SCSI_DH=y
CONFIG_SCSI_DH_RDAC=m
CONFIG_SCSI_DH_HP_SW=m
CONFIG_SCSI_DH_EMC=m
@ -205,7 +205,6 @@ CONFIG_MLX4_EN=m
# CONFIG_MLX4_DEBUG is not set
CONFIG_TEHUTI=m
CONFIG_BNX2X=m
CONFIG_QLGE=m
CONFIG_SFC=m
CONFIG_BE2NET=m
CONFIG_LIBERTAS_THINFIRM=m

2
arch/mips/configs/lemote2f_defconfig
View File

@ -39,7 +39,7 @@ CONFIG_HIBERNATION=y
CONFIG_PM_STD_PARTITION="/dev/hda3"
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEBUG=y
CONFIG_CPU_FREQ_STAT=m
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=m
CONFIG_CPU_FREQ_GOV_USERSPACE=m

4
arch/mips/configs/loongson1b_defconfig
View File

@ -74,6 +74,10 @@ CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_LOONGSON1=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_WATCHDOG_SYSFS=y
CONFIG_LOONGSON1_WDT=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_HID_GENERIC=m
CONFIG_USB_HID=m

4
arch/mips/configs/loongson1c_defconfig
View File

@ -75,6 +75,10 @@ CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_LOONGSON1=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_WATCHDOG_SYSFS=y
CONFIG_LOONGSON1_WDT=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_HID_GENERIC=m
CONFIG_USB_HID=m

4
arch/mips/configs/malta_defconfig
View File

@ -59,8 +59,8 @@ CONFIG_NETFILTER=y
CONFIG_NF_CONNTRACK=m
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CT_PROTO_DCCP=m
CONFIG_NF_CT_PROTO_UDPLITE=m
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m

4
arch/mips/configs/malta_kvm_defconfig
View File

@ -60,8 +60,8 @@ CONFIG_NETFILTER=y
CONFIG_NF_CONNTRACK=m
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CT_PROTO_DCCP=m
CONFIG_NF_CT_PROTO_UDPLITE=m
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m

4
arch/mips/configs/malta_kvm_guest_defconfig
View File

@ -59,8 +59,8 @@ CONFIG_NETFILTER=y
CONFIG_NF_CONNTRACK=m
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CT_PROTO_DCCP=m
CONFIG_NF_CT_PROTO_UDPLITE=m
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m

4
arch/mips/configs/maltaup_xpa_defconfig
View File

@ -61,8 +61,8 @@ CONFIG_NETFILTER=y
CONFIG_NF_CONNTRACK=m
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CT_PROTO_DCCP=m
CONFIG_NF_CT_PROTO_UDPLITE=m
CONFIG_NF_CT_PROTO_DCCP=y
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m

2
arch/mips/configs/nlm_xlp_defconfig
View File

@ -110,7 +110,7 @@ CONFIG_NETFILTER=y
CONFIG_NF_CONNTRACK=m
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CT_PROTO_UDPLITE=m
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m

2
arch/mips/configs/nlm_xlr_defconfig
View File

@ -90,7 +90,7 @@ CONFIG_NETFILTER=y
CONFIG_NF_CONNTRACK=m
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CT_PROTO_UDPLITE=m
CONFIG_NF_CT_PROTO_UDPLITE=y
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m

37
arch/mips/configs/xilfpga_defconfig
View File

@ -7,6 +7,12 @@ CONFIG_EMBEDDED=y
CONFIG_SLAB=y
# CONFIG_BLOCK is not set
# CONFIG_SUSPEND is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
# CONFIG_UEVENT_HELPER is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
@ -14,6 +20,30 @@ CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_FW_LOADER is not set
# CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_NETDEVICES=y
# CONFIG_NET_CORE is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_XILINX_EMACLITE=y
CONFIG_SMSC_PHY=y
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
@ -25,13 +55,18 @@ CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
# CONFIG_I2C_HELPER_AUTO is not set
CONFIG_I2C_XILINX=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_XILINX=y
# CONFIG_HWMON is not set
CONFIG_SENSORS_ADT7410=y
# CONFIG_USB_SUPPORT is not set
# CONFIG_MIPS_PLATFORM_DEVICES is not set
# CONFIG_IOMMU_SUPPORT is not set
# CONFIG_PROC_PAGE_MONITOR is not set
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_PANIC_ON_OOPS=y
# CONFIG_SCHED_DEBUG is not set

21
arch/mips/configs/xway_defconfig
View File

@ -1,12 +1,16 @@
CONFIG_LANTIQ=y
CONFIG_PCI_LANTIQ=y
CONFIG_XRX200_PHY_FW=y
CONFIG_CPU_MIPS32_R2=y
CONFIG_MIPS_MT_SMP=y
CONFIG_MIPS_VPE_LOADER=y
# CONFIG_COMPACTION is not set
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NR_CPUS=2
CONFIG_HZ_100=y
# CONFIG_SECCOMP is not set
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SYSVIPC=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_RD_GZIP is not set
@ -22,8 +26,8 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_IOSCHED_CFQ is not set
CONFIG_PCI=y
# CONFIG_COREDUMP is not set
# CONFIG_SUSPEND is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@ -35,12 +39,10 @@ CONFIG_IP_ROUTE_MULTIPATH=y
CONFIG_IP_ROUTE_VERBOSE=y
CONFIG_IP_MROUTE=y
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
CONFIG_ARPD=y
CONFIG_SYN_COOKIES=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
CONFIG_TCP_CONG_ADVANCED=y
# CONFIG_TCP_CONG_BIC is not set
@ -62,7 +64,6 @@ CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NF_CONNTRACK_IPV4=m
# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
@ -84,6 +85,8 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_LANTIQ=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_XWAY=y
CONFIG_EEPROM_93CX6=m
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
@ -91,6 +94,7 @@ CONFIG_NETDEVICES=y
CONFIG_LANTIQ_ETOP=y
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_PHYLIB=y
CONFIG_INTEL_XWAY_PHY=y
CONFIG_PPP=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MULTILINK=y
@ -111,17 +115,21 @@ CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_LANTIQ=y
CONFIG_SPI=y
CONFIG_GPIO_MM_LANTIQ=y
CONFIG_GPIO_STP_XWAY=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_LANTIQ_WDT=y
# CONFIG_HID is not set
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_DEBUG=y
CONFIG_USB_DWC2=y
CONFIG_USB_DWC2_PCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_TRIGGERS=y
@ -151,9 +159,6 @@ CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_FTRACE is not set
CONFIG_CMDLINE_BOOL=y
CONFIG_CRYPTO_MANAGER=m
CONFIG_CRYPTO_ARC4=m
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRC_ITU_T=m
CONFIG_CRC32_SARWATE=y
CONFIG_AVERAGE=y

2
arch/mips/dec/prom/identify.c
View File

@ -7,7 +7,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mc146818rtc.h>
#include <linux/module.h>
#include <linux/export.h>
#include <linux/string.h>
#include <linux/types.h>

2
arch/mips/dec/setup.c
View File

@ -9,12 +9,12 @@
* Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
*/
#include <linux/console.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqnr.h>
#include <linux/module.h>
#include <linux/param.h>
#include <linux/percpu-defs.h>
#include <linux/sched.h>

4
arch/mips/dec/wbflush.c
View File

@ -14,6 +14,7 @@
* Copyright (C) 2002 Maciej W. Rozycki
*/
#include <linux/export.h>
#include <linux/init.h>
#include <asm/bootinfo.h>
@ -88,7 +89,4 @@ static void wbflush_mips(void)
{
__fast_iob();
}
#include <linux/module.h>
EXPORT_SYMBOL(__wbflush);

2
arch/mips/emma/markeins/setup.c
View File

@ -90,7 +90,7 @@ void __init plat_time_init(void)
static void markeins_board_init(void);
extern void markeins_irq_setup(void);
static void inline __init markeins_sio_setup(void)
static inline void __init markeins_sio_setup(void)
{
}

1
arch/mips/generic/Makefile
View File

@ -13,3 +13,4 @@ obj-y += irq.o
obj-y += proc.o
obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o
obj-$(CONFIG_KEXEC) += kexec.o

13
arch/mips/generic/init.c
View File

@ -88,6 +88,19 @@ void __init *plat_get_fdt(void)
return (void *)fdt;
}
void __init plat_fdt_relocated(void *new_location)
{
/*
* reset fdt as the cached value would point to the location
* before relocations happened and update the location argument
* if it was passed using UHI
*/
fdt = NULL;
if (fw_arg0 == -2)
fw_arg1 = (unsigned long)new_location;
}
void __init plat_mem_setup(void)
{
if (mach && mach->fixup_fdt)

44
arch/mips/generic/kexec.c Normal file
View File

@ -0,0 +1,44 @@
/*
* Copyright (C) 2016 Imagination Technologies
* Author: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/kexec.h>
#include <linux/libfdt.h>
#include <linux/uaccess.h>
static int generic_kexec_prepare(struct kimage *image)
{
int i;
for (i = 0; i < image->nr_segments; i++) {
struct fdt_header fdt;
if (image->segment[i].memsz <= sizeof(fdt))
continue;
if (copy_from_user(&fdt, image->segment[i].buf, sizeof(fdt)))
continue;
if (fdt_check_header(&fdt))
continue;
kexec_args[0] = -2;
kexec_args[1] = (unsigned long)
phys_to_virt((unsigned long)image->segment[i].mem);
break;
}
return 0;
}
static int __init register_generic_kexec(void)
{
_machine_kexec_prepare = generic_kexec_prepare;
return 0;
}
arch_initcall(register_generic_kexec);

2
arch/mips/include/asm/Kbuild
View File

@ -4,6 +4,7 @@ generic-y += clkdev.h
generic-y += current.h
generic-y += dma-contiguous.h
generic-y += emergency-restart.h
generic-y += export.h
generic-y += irq_work.h
generic-y += local64.h
generic-y += mcs_spinlock.h
@ -15,6 +16,7 @@ generic-y += sections.h
generic-y += segment.h
generic-y += serial.h
generic-y += trace_clock.h
generic-y += unaligned.h
generic-y += user.h
generic-y += word-at-a-time.h
generic-y += xor.h

5
arch/mips/include/asm/asm-prototypes.h Normal file
View File

@ -0,0 +1,5 @@
#include <asm/checksum.h>
#include <asm/page.h>
#include <asm/fpu.h>
#include <asm-generic/asm-prototypes.h>
#include <asm/uaccess.h>

8
arch/mips/include/asm/asm.h
View File

@ -54,7 +54,8 @@
.align 2; \
.type symbol, @function; \
.ent symbol, 0; \
symbol: .frame sp, 0, ra
symbol: .frame sp, 0, ra; \
.insn
/*
* NESTED - declare nested routine entry point
@ -64,7 +65,8 @@ symbol: .frame sp, 0, ra
.align 2; \
.type symbol, @function; \
.ent symbol, 0; \
symbol: .frame sp, framesize, rpc
symbol: .frame sp, framesize, rpc; \
.insn
/*
* END - mark end of function
@ -86,7 +88,7 @@ symbol:
#define FEXPORT(symbol) \
.globl symbol; \
.type symbol, @function; \
symbol:
symbol: .insn
/*
* ABS - export absolute symbol

13
arch/mips/include/asm/bootinfo.h
View File

@ -164,6 +164,19 @@ static inline void plat_swiotlb_setup(void) {}
* Return: Pointer to the flattened device tree blob.
*/
extern void *plat_get_fdt(void);
#ifdef CONFIG_RELOCATABLE
/**
* plat_fdt_relocated() - Update platform's information about relocated dtb
*
* This function provides a platform-independent API to set platform's
* information about relocated DTB if it needs to be moved due to kernel
* relocation occurring at boot.
*/
void plat_fdt_relocated(void *new_location);
#endif /* CONFIG_RELOCATABLE */
#endif /* CONFIG_USE_OF */
#endif /* _ASM_BOOTINFO_H */

2
arch/mips/include/asm/checksum.h
View File

@ -186,7 +186,9 @@ static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
" daddu %0, %4 \n"
" dsll32 $1, %0, 0 \n"
" daddu %0, $1 \n"
" sltu $1, %0, $1 \n"
" dsra32 %0, %0, 0 \n"
" addu %0, $1 \n"
#endif
" .set pop"
: "=r" (sum)

9
arch/mips/include/asm/elf.h
View File

@ -210,6 +210,9 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef double elf_fpreg_t;
typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
void mips_dump_regs32(u32 *uregs, const struct pt_regs *regs);
void mips_dump_regs64(u64 *uregs, const struct pt_regs *regs);
#ifdef CONFIG_32BIT
/*
* This is used to ensure we don't load something for the wrong architecture.
@ -221,6 +224,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
*/
#define ELF_CLASS ELFCLASS32
#define ELF_CORE_COPY_REGS(dest, regs) \
mips_dump_regs32((u32 *)&(dest), (regs));
#endif /* CONFIG_32BIT */
#ifdef CONFIG_64BIT
@ -234,6 +240,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
*/
#define ELF_CLASS ELFCLASS64
#define ELF_CORE_COPY_REGS(dest, regs) \
mips_dump_regs64((u64 *)&(dest), (regs));
#endif /* CONFIG_64BIT */
/*

3
arch/mips/include/asm/highmem.h
View File

@ -25,9 +25,6 @@
#include <asm/cpu-features.h>
#include <asm/kmap_types.h>
/* undef for production */
#define HIGHMEM_DEBUG 1
/* declarations for highmem.c */
extern unsigned long highstart_pfn, highend_pfn;

1
arch/mips/include/asm/i8259.h
View File

@ -40,7 +40,6 @@ extern raw_spinlock_t i8259A_lock;
extern void make_8259A_irq(unsigned int irq);
extern void init_i8259_irqs(void);
extern int i8259_of_init(struct device_node *node, struct device_node *parent);
/**
* i8159_set_poll() - Override the i8259 polling function

12
arch/mips/include/asm/irq.h
View File

@ -17,6 +17,18 @@
#include <irq.h>
#define IRQ_STACK_SIZE THREAD_SIZE
extern void *irq_stack[NR_CPUS];
static inline bool on_irq_stack(int cpu, unsigned long sp)
{
unsigned long low = (unsigned long)irq_stack[cpu];
unsigned long high = low + IRQ_STACK_SIZE;
return (low <= sp && sp <= high);
}
#ifdef CONFIG_I8259
static inline int irq_canonicalize(int irq)
{

9
arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
View File

@ -80,6 +80,15 @@ enum bcm47xx_board {
BCM47XX_BOARD_LINKSYS_WRT610NV2,
BCM47XX_BOARD_LINKSYS_WRTSL54GS,
BCM47XX_BOARD_LUXUL_ABR_4400_V1,
BCM47XX_BOARD_LUXUL_XAP_310_V1,
BCM47XX_BOARD_LUXUL_XAP_1210_V1,
BCM47XX_BOARD_LUXUL_XAP_1230_V1,
BCM47XX_BOARD_LUXUL_XAP_1240_V1,
BCM47XX_BOARD_LUXUL_XAP_1500_V1,
BCM47XX_BOARD_LUXUL_XBR_4400_V1,
BCM47XX_BOARD_LUXUL_XVW_P30_V1,
BCM47XX_BOARD_LUXUL_XWR_600_V1,
BCM47XX_BOARD_LUXUL_XWR_1750_V1,
BCM47XX_BOARD_MICROSOFT_MN700,

15
arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
View File

@ -99,9 +99,20 @@
# to begin
#
# This is the variable where the next core to boot os stored
PTR_LA t0, octeon_processor_boot
octeon_spin_wait_boot:
#ifdef CONFIG_RELOCATABLE
PTR_LA t0, octeon_processor_relocated_kernel_entry
LONG_L t0, (t0)
beq zero, t0, 1f
nop
jr t0
nop
1:
#endif /* CONFIG_RELOCATABLE */
# This is the variable where the next core to boot is stored
PTR_LA t0, octeon_processor_boot
# Get the core id of the next to be booted
LONG_L t1, (t0)
# Keep looping if it isn't me

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