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MIPS: Alchemy: add sysdev for IRQ PM.
Use a sysdev to implement PM methods for the Au1000 interrupt controllers. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1114/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
Ralf Baechle
parent
7b5fcd694d
commit
0f0d85bcc3
3 changed files with 122 additions and 91 deletions
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@ -29,6 +29,8 @@
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/slab.h>
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#include <linux/sysdev.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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@ -216,90 +218,6 @@ struct au1xxx_irqmap au1200_irqmap[] __initdata = {
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};
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#ifdef CONFIG_PM
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/*
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* Save/restore the interrupt controller state.
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* Called from the save/restore core registers as part of the
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* au_sleep function in power.c.....maybe I should just pm_register()
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* them instead?
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*/
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static unsigned int sleep_intctl_config0[2];
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static unsigned int sleep_intctl_config1[2];
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static unsigned int sleep_intctl_config2[2];
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static unsigned int sleep_intctl_src[2];
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static unsigned int sleep_intctl_assign[2];
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static unsigned int sleep_intctl_wake[2];
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static unsigned int sleep_intctl_mask[2];
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void save_au1xxx_intctl(void)
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{
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sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
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sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
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sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
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sleep_intctl_src[0] = au_readl(IC0_SRCRD);
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sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
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sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
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sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
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sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
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sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
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sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
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sleep_intctl_src[1] = au_readl(IC1_SRCRD);
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sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
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sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
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sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
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}
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/*
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* For most restore operations, we clear the entire register and
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* then set the bits we found during the save.
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*/
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void restore_au1xxx_intctl(void)
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{
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au_writel(0xffffffff, IC0_MASKCLR); au_sync();
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au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
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au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
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au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
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au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
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au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
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au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
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au_writel(0xffffffff, IC0_SRCCLR); au_sync();
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au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
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au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
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au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
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au_writel(0xffffffff, IC0_WAKECLR); au_sync();
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au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
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au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
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au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
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au_writel(0x00000000, IC0_TESTBIT); au_sync();
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au_writel(0xffffffff, IC1_MASKCLR); au_sync();
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au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
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au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
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au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
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au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
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au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
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au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
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au_writel(0xffffffff, IC1_SRCCLR); au_sync();
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au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
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au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
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au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
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au_writel(0xffffffff, IC1_WAKECLR); au_sync();
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au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
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au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
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au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
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au_writel(0x00000000, IC1_TESTBIT); au_sync();
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au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
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au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
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}
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#endif /* CONFIG_PM */
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static void au1x_ic0_unmask(unsigned int irq_nr)
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{
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unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
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@ -635,3 +553,91 @@ void __init arch_init_irq(void)
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break;
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}
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}
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struct alchemy_ic_sysdev {
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struct sys_device sysdev;
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void __iomem *base;
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unsigned long pmdata[7];
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};
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static int alchemy_ic_suspend(struct sys_device *dev, pm_message_t state)
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{
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struct alchemy_ic_sysdev *icdev =
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container_of(dev, struct alchemy_ic_sysdev, sysdev);
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icdev->pmdata[0] = __raw_readl(icdev->base + IC_CFG0RD);
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icdev->pmdata[1] = __raw_readl(icdev->base + IC_CFG1RD);
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icdev->pmdata[2] = __raw_readl(icdev->base + IC_CFG2RD);
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icdev->pmdata[3] = __raw_readl(icdev->base + IC_SRCRD);
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icdev->pmdata[4] = __raw_readl(icdev->base + IC_ASSIGNRD);
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icdev->pmdata[5] = __raw_readl(icdev->base + IC_WAKERD);
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icdev->pmdata[6] = __raw_readl(icdev->base + IC_MASKRD);
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return 0;
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}
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static int alchemy_ic_resume(struct sys_device *dev)
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{
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struct alchemy_ic_sysdev *icdev =
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container_of(dev, struct alchemy_ic_sysdev, sysdev);
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__raw_writel(0xffffffff, icdev->base + IC_MASKCLR);
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__raw_writel(0xffffffff, icdev->base + IC_CFG0CLR);
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__raw_writel(0xffffffff, icdev->base + IC_CFG1CLR);
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__raw_writel(0xffffffff, icdev->base + IC_CFG2CLR);
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__raw_writel(0xffffffff, icdev->base + IC_SRCCLR);
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__raw_writel(0xffffffff, icdev->base + IC_ASSIGNCLR);
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__raw_writel(0xffffffff, icdev->base + IC_WAKECLR);
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__raw_writel(0xffffffff, icdev->base + IC_RISINGCLR);
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__raw_writel(0xffffffff, icdev->base + IC_FALLINGCLR);
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__raw_writel(0x00000000, icdev->base + IC_TESTBIT);
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wmb();
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__raw_writel(icdev->pmdata[0], icdev->base + IC_CFG0SET);
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__raw_writel(icdev->pmdata[1], icdev->base + IC_CFG1SET);
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__raw_writel(icdev->pmdata[2], icdev->base + IC_CFG2SET);
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__raw_writel(icdev->pmdata[3], icdev->base + IC_SRCSET);
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__raw_writel(icdev->pmdata[4], icdev->base + IC_ASSIGNSET);
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__raw_writel(icdev->pmdata[5], icdev->base + IC_WAKESET);
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wmb();
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__raw_writel(icdev->pmdata[6], icdev->base + IC_MASKSET);
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wmb();
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return 0;
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}
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static struct sysdev_class alchemy_ic_sysdev_class = {
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.name = "ic",
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.suspend = alchemy_ic_suspend,
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.resume = alchemy_ic_resume,
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};
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static int __init alchemy_ic_sysdev_init(void)
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{
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struct alchemy_ic_sysdev *icdev;
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unsigned long icbase[2] = { IC0_PHYS_ADDR, IC1_PHYS_ADDR };
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int err, i;
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err = sysdev_class_register(&alchemy_ic_sysdev_class);
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if (err)
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return err;
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for (i = 0; i < 2; i++) {
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icdev = kzalloc(sizeof(struct alchemy_ic_sysdev), GFP_KERNEL);
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if (!icdev)
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return -ENOMEM;
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icdev->base = ioremap(icbase[i], 0x1000);
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icdev->sysdev.id = i;
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icdev->sysdev.cls = &alchemy_ic_sysdev_class;
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err = sysdev_register(&icdev->sysdev);
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if (err) {
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kfree(icdev);
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return err;
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}
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}
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return 0;
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}
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device_initcall(alchemy_ic_sysdev_init);
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@ -106,9 +106,6 @@ static void save_core_regs(void)
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sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */
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#endif
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/* Save interrupt controller state. */
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save_au1xxx_intctl();
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/* Clocks and PLLs. */
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sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
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sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
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@ -200,8 +197,6 @@ static void restore_core_regs(void)
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au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync();
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}
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restore_au1xxx_intctl();
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#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
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au1xxx_dbdma_resume();
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#endif
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@ -190,8 +190,6 @@ extern unsigned long au1xxx_calc_clock(void);
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/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
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void au1xxx_save_and_sleep(void);
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void au_sleep(void);
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void save_au1xxx_intctl(void);
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void restore_au1xxx_intctl(void);
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/* SOC Interrupt numbers */
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@ -835,6 +833,38 @@ enum soc_au1200_ints {
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#define MEM_STNAND_DATA 0x20
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#endif
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/* Interrupt Controller register offsets */
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#define IC_CFG0RD 0x40
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#define IC_CFG0SET 0x40
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#define IC_CFG0CLR 0x44
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#define IC_CFG1RD 0x48
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#define IC_CFG1SET 0x48
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#define IC_CFG1CLR 0x4C
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#define IC_CFG2RD 0x50
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#define IC_CFG2SET 0x50
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#define IC_CFG2CLR 0x54
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#define IC_REQ0INT 0x54
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#define IC_SRCRD 0x58
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#define IC_SRCSET 0x58
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#define IC_SRCCLR 0x5C
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#define IC_REQ1INT 0x5C
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#define IC_ASSIGNRD 0x60
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#define IC_ASSIGNSET 0x60
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#define IC_ASSIGNCLR 0x64
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#define IC_WAKERD 0x68
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#define IC_WAKESET 0x68
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#define IC_WAKECLR 0x6C
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#define IC_MASKRD 0x70
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#define IC_MASKSET 0x70
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#define IC_MASKCLR 0x74
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#define IC_RISINGRD 0x78
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#define IC_RISINGCLR 0x78
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#define IC_FALLINGRD 0x7C
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#define IC_FALLINGCLR 0x7C
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#define IC_TESTBIT 0x80
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/* Interrupt Controller 0 */
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#define IC0_CFG0RD 0xB0400040
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#define IC0_CFG0SET 0xB0400040
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