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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 01:10:04 +00:00
drm/i915: Pass dev_priv to intel_wait_for_vblank()
Unify our approach to things by passing around dev_priv instead of dev. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1477946245-14134-8-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
parent
e2af48c66b
commit
0f0f74bc83
8 changed files with 38 additions and 36 deletions
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@ -4211,7 +4211,7 @@ static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
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drm_modeset_lock(&crtc->base.mutex, NULL);
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if (crtc->base.state->active)
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intel_wait_for_vblank(dev, pipe);
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intel_wait_for_vblank(dev_priv, pipe);
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drm_modeset_unlock(&crtc->base.mutex);
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spin_lock_irq(&pipe_crc->lock);
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@ -573,7 +573,7 @@ intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe)
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POSTING_READ(pipeconf_reg);
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/* Wait for next Vblank to substitue
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* border color for Color info */
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intel_wait_for_vblank(dev, pipe);
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intel_wait_for_vblank(dev_priv, pipe);
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st00 = I915_READ8(_VGA_MSR_WRITE);
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status = ((st00 & (1 << 4)) != 0) ?
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connector_status_connected :
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@ -4249,6 +4249,7 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
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bool intel_has_pending_fb_unpin(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *crtc;
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/* Note that we don't need to be called with mode_config.lock here
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@ -4263,7 +4264,7 @@ bool intel_has_pending_fb_unpin(struct drm_device *dev)
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continue;
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if (crtc->flip_work)
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intel_wait_for_vblank(dev, crtc->pipe);
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intel_wait_for_vblank(dev_priv, crtc->pipe);
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return true;
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}
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@ -4940,7 +4941,7 @@ void hsw_disable_ips(struct intel_crtc *crtc)
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}
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/* We need to wait for a vblank before we can disable the plane. */
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intel_wait_for_vblank(dev, crtc->pipe);
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intel_wait_for_vblank(dev_priv, crtc->pipe);
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}
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static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
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@ -5052,7 +5053,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
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if (HAS_GMCH_DISPLAY(dev_priv)) {
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intel_set_memory_cxsr(dev_priv, false);
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dev_priv->wm.vlv.cxsr = false;
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intel_wait_for_vblank(dev, pipe);
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intel_wait_for_vblank(dev_priv, pipe);
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}
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}
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@ -5129,7 +5130,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
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if (old_crtc_state->base.active) {
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intel_set_memory_cxsr(dev_priv, false);
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dev_priv->wm.vlv.cxsr = false;
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intel_wait_for_vblank(dev, crtc->pipe);
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intel_wait_for_vblank(dev_priv, crtc->pipe);
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}
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}
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@ -5142,7 +5143,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
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*/
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if (pipe_config->disable_lp_wm) {
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ilk_disable_lp_wm(dev);
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intel_wait_for_vblank(dev, crtc->pipe);
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intel_wait_for_vblank(dev_priv, crtc->pipe);
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}
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/*
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@ -5397,7 +5398,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
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/* Must wait for vblank to avoid spurious PCH FIFO underruns */
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if (intel_crtc->config->has_pch_encoder)
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intel_wait_for_vblank(dev, pipe);
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intel_wait_for_vblank(dev_priv, pipe);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
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intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
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}
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@ -5507,8 +5508,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
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intel_encoders_enable(crtc, pipe_config, old_state);
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if (intel_crtc->config->has_pch_encoder) {
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intel_wait_for_vblank(dev, pipe);
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intel_wait_for_vblank(dev, pipe);
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intel_wait_for_vblank(dev_priv, pipe);
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intel_wait_for_vblank(dev_priv, pipe);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
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intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
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true);
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@ -5518,8 +5519,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
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* to change the workaround. */
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hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
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if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
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intel_wait_for_vblank(dev, hsw_workaround_pipe);
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intel_wait_for_vblank(dev, hsw_workaround_pipe);
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intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
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intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
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}
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}
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@ -6833,7 +6834,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
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* wait for planes to fully turn off before disabling the pipe.
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*/
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if (IS_GEN2(dev_priv))
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intel_wait_for_vblank(dev, pipe);
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intel_wait_for_vblank(dev_priv, pipe);
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intel_encoders_disable(crtc, old_crtc_state, old_state);
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@ -11129,6 +11130,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
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struct drm_encoder *encoder = &intel_encoder->base;
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struct drm_crtc *crtc = NULL;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_framebuffer *fb;
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struct drm_mode_config *config = &dev->mode_config;
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struct drm_atomic_state *state = NULL, *restore_state = NULL;
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@ -11281,7 +11283,7 @@ bool intel_get_load_detect_pipe(struct drm_connector *connector,
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old->restore_state = restore_state;
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/* let the connector get through one full cycle before testing */
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intel_wait_for_vblank(dev, intel_crtc->pipe);
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intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
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return true;
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fail:
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@ -14277,7 +14279,7 @@ static void intel_update_crtcs(struct drm_atomic_state *state,
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static void skl_update_crtcs(struct drm_atomic_state *state,
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unsigned int *crtc_vblank_mask)
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{
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struct drm_device *dev = state->dev;
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struct drm_i915_private *dev_priv = to_i915(state->dev);
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struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
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struct drm_crtc *crtc;
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struct intel_crtc *intel_crtc;
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@ -14328,7 +14330,7 @@ static void skl_update_crtcs(struct drm_atomic_state *state,
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crtc_vblank_mask);
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if (vbl_wait)
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intel_wait_for_vblank(dev, pipe);
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intel_wait_for_vblank(dev_priv, pipe);
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progress = true;
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}
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@ -2364,7 +2364,7 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
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* 2. Program DP PLL enable
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*/
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if (IS_GEN5(dev_priv))
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intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe);
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intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
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intel_dp->DP |= DP_PLL_ENABLE;
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@ -3487,7 +3487,7 @@ intel_dp_link_down(struct intel_dp *intel_dp)
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I915_WRITE(intel_dp->output_reg, DP);
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POSTING_READ(intel_dp->output_reg);
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intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
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intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
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intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
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}
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@ -3667,7 +3667,7 @@ intel_dp_configure_mst(struct intel_dp *intel_dp)
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static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
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u8 buf;
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int ret = 0;
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@ -3688,7 +3688,7 @@ static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
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}
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do {
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intel_wait_for_vblank(dev, intel_crtc->pipe);
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intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
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if (drm_dp_dpcd_readb(&intel_dp->aux,
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DP_TEST_SINK_MISC, &buf) < 0) {
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@ -3711,7 +3711,7 @@ static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
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static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
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u8 buf;
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int ret;
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@ -3739,14 +3739,14 @@ static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
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return -EIO;
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}
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intel_wait_for_vblank(dev, intel_crtc->pipe);
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intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
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return 0;
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}
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int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
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u8 buf;
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int count, ret;
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@ -3757,7 +3757,7 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
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return ret;
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do {
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intel_wait_for_vblank(dev, intel_crtc->pipe);
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intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
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if (drm_dp_dpcd_readb(&intel_dp->aux,
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DP_TEST_SINK_MISC, &buf) < 0) {
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@ -3990,7 +3990,7 @@ intel_dp_retrain_link(struct intel_dp *intel_dp)
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intel_dp_stop_link_train(intel_dp);
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/* Keep underrun reporting disabled until things are stable */
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intel_wait_for_vblank(&dev_priv->drm, crtc->pipe);
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intel_wait_for_vblank(dev_priv, crtc->pipe);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
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if (crtc->config->has_pch_encoder)
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@ -1244,17 +1244,17 @@ intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
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(1 << INTEL_OUTPUT_EDP));
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}
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static inline void
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intel_wait_for_vblank(struct drm_device *dev, int pipe)
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intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
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{
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drm_wait_one_vblank(dev, pipe);
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drm_wait_one_vblank(&dev_priv->drm, pipe);
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}
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static inline void
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intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
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intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
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{
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const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev, pipe);
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const struct intel_crtc *crtc = intel_get_crtc_for_pipe(&dev_priv->drm, pipe);
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if (crtc->active)
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intel_wait_for_vblank(dev, pipe);
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intel_wait_for_vblank(dev_priv, pipe);
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}
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u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
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@ -1164,7 +1164,7 @@ static void intel_disable_hdmi(struct intel_encoder *encoder,
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I915_WRITE(intel_hdmi->hdmi_reg, temp);
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POSTING_READ(intel_hdmi->hdmi_reg);
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intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
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intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
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intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
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}
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@ -1472,7 +1472,7 @@ static void intel_disable_sdvo(struct intel_encoder *encoder,
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temp &= ~SDVO_ENABLE;
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intel_sdvo_write_sdvox(intel_sdvo, temp);
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intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
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intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
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intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
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intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
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}
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@ -1509,7 +1509,7 @@ static void intel_enable_sdvo(struct intel_encoder *encoder,
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intel_sdvo_write_sdvox(intel_sdvo, temp);
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for (i = 0; i < 2; i++)
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intel_wait_for_vblank(dev, intel_crtc->pipe);
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intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
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success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
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/* Warn if the device reported failure to sync.
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@ -856,7 +856,7 @@ intel_enable_tv(struct intel_encoder *encoder,
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struct drm_i915_private *dev_priv = to_i915(dev);
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/* Prevents vblank waits from timing out in intel_tv_detect_type() */
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intel_wait_for_vblank(encoder->base.dev,
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intel_wait_for_vblank(dev_priv,
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to_intel_crtc(encoder->base.crtc)->pipe);
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I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
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@ -1238,7 +1238,7 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
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I915_WRITE(TV_DAC, tv_dac);
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POSTING_READ(TV_DAC);
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intel_wait_for_vblank(dev, intel_crtc->pipe);
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intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
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type = -1;
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tv_dac = I915_READ(TV_DAC);
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POSTING_READ(TV_CTL);
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/* For unknown reasons the hw barfs if we don't do this vblank wait. */
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intel_wait_for_vblank(dev, intel_crtc->pipe);
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intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
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/* Restore interrupt config */
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if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
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