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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 03:10:12 +00:00
ASoC: tegra: use regmap more directly
Stop open-coding the caching of the ctrl registers; instead, use regmap_update_bits() to update parts of the register from different places. The removal of the open-coded cache will allow controls to be created which touch registers, which will be necessary if any of these modules are converted to CODECs. Get rid of tegra*_read/write; just call regmap_read/write directly. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
parent
c92a40e3a1
commit
0f163546a7
6 changed files with 95 additions and 112 deletions
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@ -46,18 +46,6 @@
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#define DRV_NAME "tegra20-i2s"
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static inline void tegra20_i2s_write(struct tegra20_i2s *i2s, u32 reg, u32 val)
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{
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regmap_write(i2s->regmap, reg, val);
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}
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static inline u32 tegra20_i2s_read(struct tegra20_i2s *i2s, u32 reg)
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{
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u32 val;
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regmap_read(i2s->regmap, reg, &val);
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return val;
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}
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static int tegra20_i2s_runtime_suspend(struct device *dev)
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{
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struct tegra20_i2s *i2s = dev_get_drvdata(dev);
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@ -85,6 +73,7 @@ static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai,
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unsigned int fmt)
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{
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struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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unsigned int mask, val;
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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@ -93,10 +82,10 @@ static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai,
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return -EINVAL;
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}
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i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_MASTER_ENABLE;
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mask = TEGRA20_I2S_CTRL_MASTER_ENABLE;
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_MASTER_ENABLE;
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val = TEGRA20_I2S_CTRL_MASTER_ENABLE;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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break;
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@ -104,33 +93,35 @@ static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai,
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return -EINVAL;
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}
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i2s->reg_ctrl &= ~(TEGRA20_I2S_CTRL_BIT_FORMAT_MASK |
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TEGRA20_I2S_CTRL_LRCK_MASK);
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mask |= TEGRA20_I2S_CTRL_BIT_FORMAT_MASK |
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TEGRA20_I2S_CTRL_LRCK_MASK;
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_DSP_A:
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
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val |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
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val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
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break;
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case SND_SOC_DAIFMT_DSP_B:
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_R_LOW;
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val |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
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val |= TEGRA20_I2S_CTRL_LRCK_R_LOW;
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break;
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case SND_SOC_DAIFMT_I2S:
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S;
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
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val |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S;
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val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM;
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
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val |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM;
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val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM;
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
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val |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM;
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val |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val);
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return 0;
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}
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@ -140,27 +131,32 @@ static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream,
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{
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struct device *dev = dai->dev;
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struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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u32 reg;
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unsigned int mask, val;
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int ret, sample_size, srate, i2sclock, bitcnt;
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i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_BIT_SIZE_MASK;
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mask = TEGRA20_I2S_CTRL_BIT_SIZE_MASK;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_16;
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val = TEGRA20_I2S_CTRL_BIT_SIZE_16;
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sample_size = 16;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_24;
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val = TEGRA20_I2S_CTRL_BIT_SIZE_24;
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sample_size = 24;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_32;
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val = TEGRA20_I2S_CTRL_BIT_SIZE_32;
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sample_size = 32;
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break;
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default:
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return -EINVAL;
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}
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mask |= TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK;
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val |= TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED;
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regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL, mask, val);
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srate = params_rate(params);
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/* Final "* 2" required by Tegra hardware */
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@ -175,42 +171,44 @@ static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream,
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bitcnt = (i2sclock / (2 * srate)) - 1;
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if (bitcnt < 0 || bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
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return -EINVAL;
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reg = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
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val = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
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if (i2sclock % (2 * srate))
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reg |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE;
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val |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE;
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tegra20_i2s_write(i2s, TEGRA20_I2S_TIMING, reg);
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regmap_write(i2s->regmap, TEGRA20_I2S_TIMING, val);
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tegra20_i2s_write(i2s, TEGRA20_I2S_FIFO_SCR,
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TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
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TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
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regmap_write(i2s->regmap, TEGRA20_I2S_FIFO_SCR,
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TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
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TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
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return 0;
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}
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static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s)
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{
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO1_ENABLE;
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tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
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regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
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TEGRA20_I2S_CTRL_FIFO1_ENABLE,
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TEGRA20_I2S_CTRL_FIFO1_ENABLE);
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}
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static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s)
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{
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i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO1_ENABLE;
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tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
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regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
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TEGRA20_I2S_CTRL_FIFO1_ENABLE, 0);
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}
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static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s)
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{
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i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO2_ENABLE;
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tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
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regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
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TEGRA20_I2S_CTRL_FIFO2_ENABLE,
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TEGRA20_I2S_CTRL_FIFO2_ENABLE);
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}
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static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s)
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{
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i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO2_ENABLE;
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tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
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regmap_update_bits(i2s->regmap, TEGRA20_I2S_CTRL,
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TEGRA20_I2S_CTRL_FIFO2_ENABLE, 0);
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}
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static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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@ -414,8 +412,6 @@ static __devinit int tegra20_i2s_platform_probe(struct platform_device *pdev)
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i2s->playback_dma_data.width = 32;
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i2s->playback_dma_data.req_sel = dma_ch;
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i2s->reg_ctrl = TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED;
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pm_runtime_enable(&pdev->dev);
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if (!pm_runtime_enabled(&pdev->dev)) {
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ret = tegra20_i2s_runtime_resume(&pdev->dev);
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@ -158,7 +158,6 @@ struct tegra20_i2s {
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struct tegra_pcm_dma_params capture_dma_data;
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struct tegra_pcm_dma_params playback_dma_data;
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struct regmap *regmap;
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u32 reg_ctrl;
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};
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#endif
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@ -37,19 +37,6 @@
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#define DRV_NAME "tegra20-spdif"
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static inline void tegra20_spdif_write(struct tegra20_spdif *spdif, u32 reg,
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u32 val)
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{
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regmap_write(spdif->regmap, reg, val);
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}
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static inline u32 tegra20_spdif_read(struct tegra20_spdif *spdif, u32 reg)
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{
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u32 val;
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regmap_read(spdif->regmap, reg, &val);
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return val;
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}
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static int tegra20_spdif_runtime_suspend(struct device *dev)
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{
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struct tegra20_spdif *spdif = dev_get_drvdata(dev);
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{
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struct device *dev = dai->dev;
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struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai);
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unsigned int mask, val;
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int ret, spdifclock;
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spdif->reg_ctrl &= ~TEGRA20_SPDIF_CTRL_PACK;
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spdif->reg_ctrl &= ~TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
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mask = TEGRA20_SPDIF_CTRL_PACK |
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TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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spdif->reg_ctrl |= TEGRA20_SPDIF_CTRL_PACK;
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spdif->reg_ctrl |= TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
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val = TEGRA20_SPDIF_CTRL_PACK |
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TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
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break;
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default:
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return -EINVAL;
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}
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regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val);
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switch (params_rate(params)) {
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case 32000:
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spdifclock = 4096000;
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static void tegra20_spdif_start_playback(struct tegra20_spdif *spdif)
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{
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spdif->reg_ctrl |= TEGRA20_SPDIF_CTRL_TX_EN;
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tegra20_spdif_write(spdif, TEGRA20_SPDIF_CTRL, spdif->reg_ctrl);
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regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
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TEGRA20_SPDIF_CTRL_TX_EN,
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TEGRA20_SPDIF_CTRL_TX_EN);
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}
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static void tegra20_spdif_stop_playback(struct tegra20_spdif *spdif)
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{
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spdif->reg_ctrl &= ~TEGRA20_SPDIF_CTRL_TX_EN;
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tegra20_spdif_write(spdif, TEGRA20_SPDIF_CTRL, spdif->reg_ctrl);
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regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
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TEGRA20_SPDIF_CTRL_TX_EN, 0);
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}
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static int tegra20_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
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struct tegra_pcm_dma_params capture_dma_data;
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struct tegra_pcm_dma_params playback_dma_data;
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struct regmap *regmap;
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u32 reg_ctrl;
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};
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#endif
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@ -44,18 +44,6 @@
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#define DRV_NAME "tegra30-i2s"
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static inline void tegra30_i2s_write(struct tegra30_i2s *i2s, u32 reg, u32 val)
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{
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regmap_write(i2s->regmap, reg, val);
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}
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static inline u32 tegra30_i2s_read(struct tegra30_i2s *i2s, u32 reg)
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{
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u32 val;
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regmap_read(i2s->regmap, reg, &val);
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return val;
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}
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static int tegra30_i2s_runtime_suspend(struct device *dev)
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{
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struct tegra30_i2s *i2s = dev_get_drvdata(dev);
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@ -128,6 +116,7 @@ static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
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unsigned int fmt)
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{
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struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
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unsigned int mask, val;
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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@ -136,10 +125,10 @@ static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
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return -EINVAL;
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}
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i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_MASTER_ENABLE;
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mask = TEGRA30_I2S_CTRL_MASTER_ENABLE;
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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i2s->reg_ctrl |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
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val = TEGRA30_I2S_CTRL_MASTER_ENABLE;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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break;
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@ -147,33 +136,37 @@ static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
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return -EINVAL;
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}
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i2s->reg_ctrl &= ~(TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
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TEGRA30_I2S_CTRL_LRCK_MASK);
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mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
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TEGRA30_I2S_CTRL_LRCK_MASK;
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_DSP_A:
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i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
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i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
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val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
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val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
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break;
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case SND_SOC_DAIFMT_DSP_B:
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i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
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i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
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val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
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val |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
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break;
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case SND_SOC_DAIFMT_I2S:
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i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
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i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
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val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
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val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
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i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
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val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
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val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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i2s->reg_ctrl |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
|
||||
i2s->reg_ctrl |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
|
||||
val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
|
||||
val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pm_runtime_get_sync(dai->dev);
|
||||
regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
|
||||
pm_runtime_put(dai->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -183,22 +176,24 @@ static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
|
|||
{
|
||||
struct device *dev = dai->dev;
|
||||
struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
|
||||
u32 val;
|
||||
unsigned int mask, val, reg;
|
||||
int ret, sample_size, srate, i2sclock, bitcnt;
|
||||
|
||||
if (params_channels(params) != 2)
|
||||
return -EINVAL;
|
||||
|
||||
i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
|
||||
mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
i2s->reg_ctrl |= TEGRA30_I2S_CTRL_BIT_SIZE_16;
|
||||
val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
|
||||
sample_size = 16;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
|
||||
|
||||
srate = params_rate(params);
|
||||
|
||||
/* Final "* 2" required by Tegra hardware */
|
||||
|
@ -219,7 +214,7 @@ static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
|
|||
if (i2sclock % (2 * srate))
|
||||
val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
|
||||
|
||||
tegra30_i2s_write(i2s, TEGRA30_I2S_TIMING, val);
|
||||
regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
|
||||
|
||||
val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
|
||||
(1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
|
||||
|
@ -229,15 +224,17 @@ static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
|
|||
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
||||
val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
|
||||
tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_RX_CTRL, val);
|
||||
reg = TEGRA30_I2S_CIF_RX_CTRL;
|
||||
} else {
|
||||
val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
|
||||
tegra30_i2s_write(i2s, TEGRA30_I2S_CIF_TX_CTRL, val);
|
||||
reg = TEGRA30_I2S_CIF_RX_CTRL;
|
||||
}
|
||||
|
||||
regmap_write(i2s->regmap, reg, val);
|
||||
|
||||
val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
|
||||
(1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
|
||||
tegra30_i2s_write(i2s, TEGRA30_I2S_OFFSET, val);
|
||||
regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -245,29 +242,31 @@ static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
|
|||
static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
|
||||
{
|
||||
tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
|
||||
i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_TX;
|
||||
tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
|
||||
regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
|
||||
TEGRA30_I2S_CTRL_XFER_EN_TX,
|
||||
TEGRA30_I2S_CTRL_XFER_EN_TX);
|
||||
}
|
||||
|
||||
static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
|
||||
{
|
||||
tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
|
||||
i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_TX;
|
||||
tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
|
||||
regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
|
||||
TEGRA30_I2S_CTRL_XFER_EN_TX, 0);
|
||||
}
|
||||
|
||||
static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
|
||||
{
|
||||
tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
|
||||
i2s->reg_ctrl |= TEGRA30_I2S_CTRL_XFER_EN_RX;
|
||||
tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
|
||||
regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
|
||||
TEGRA30_I2S_CTRL_XFER_EN_RX,
|
||||
TEGRA30_I2S_CTRL_XFER_EN_RX);
|
||||
}
|
||||
|
||||
static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
|
||||
{
|
||||
tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
|
||||
i2s->reg_ctrl &= ~TEGRA30_I2S_CTRL_XFER_EN_RX;
|
||||
tegra30_i2s_write(i2s, TEGRA30_I2S_CTRL, i2s->reg_ctrl);
|
||||
regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
|
||||
TEGRA30_I2S_CTRL_XFER_EN_RX, 0);
|
||||
}
|
||||
|
||||
static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
|
||||
|
|
|
@ -236,7 +236,6 @@ struct tegra30_i2s {
|
|||
enum tegra30_ahub_txcif playback_fifo_cif;
|
||||
struct tegra_pcm_dma_params playback_dma_data;
|
||||
struct regmap *regmap;
|
||||
u32 reg_ctrl;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
Loading…
Reference in a new issue