ARM: gemini: add device tree for ssi1328
The SSI 1328 is a NAS box running a SL3516 SoC. Signed-off-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -223,6 +223,7 @@ dtb-$(CONFIG_ARCH_GEMINI) += \
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gemini-rut1xx.dtb \
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gemini-sl93512r.dtb \
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gemini-sq201.dtb \
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gemini-ssi1328.dtb \
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gemini-wbd111.dtb \
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gemini-wbd222.dtb
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dtb-$(CONFIG_ARCH_HI3xxx) += \
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@ -0,0 +1,138 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Corentin Labbe <clabbe@baylibre.com>
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* Device Tree file for SSI 1328
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*/
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/dts-v1/;
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#include "gemini.dtsi"
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/ {
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model = "SSI 1328";
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compatible = "ssi,1328", "cortina,gemini";
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#address-cells = <1>;
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#size-cells = <1>;
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memory@0 {
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/* 128 MB */
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device_type = "memory";
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reg = <0x00000000 0x8000000>;
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};
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aliases {
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mdio-gpio0 = &mdio0;
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};
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chosen {
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bootargs = "console=ttyS0,19200n8 initrd=0x900000,9M";
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stdout-path = &uart0;
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};
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mdio0: mdio {
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compatible = "virtual,mdio-gpio";
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gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
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<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
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#address-cells = <1>;
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#size-cells = <0>;
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/* LAN Marvell 88E1118 */
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phy0: ethernet-phy@1 {
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reg = <1>;
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device_type = "ethernet-phy";
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/* We lack the knowledge of necessary GPIO to achieve
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* Gigabit
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*/
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max-speed = <100>;
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};
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/* WAN ICPlus IP101A */
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phy1: ethernet-phy@2 {
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reg = <2>;
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device_type = "ethernet-phy";
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};
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};
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};
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ðernet {
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status = "okay";
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ethernet-port@0 {
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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};
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ethernet-port@1 {
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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};
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};
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&flash {
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status = "okay";
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/* 32MB of flash */
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reg = <0x30000000 0x03200000>;
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pinctrl-names = "enabled", "disabled";
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pinctrl-0 = <&pflash_default_pins>;
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pinctrl-1 = <&pflash_disabled_pins>;
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partitions {
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compatible = "redboot-fis";
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/* Eraseblock at 0xfe0000 */
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fis-index-block = <0x7F>;
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};
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};
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&gpio0 {
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pinctrl-names = "default";
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pinctrl-0 = <&gpio0_default_pins>;
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};
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&ide0 {
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status = "okay";
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};
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&ide1 {
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status = "okay";
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};
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&sata {
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cortina,gemini-ata-muxmode = <0>;
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cortina,gemini-enable-sata-bridge;
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status = "okay";
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};
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&syscon {
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pinctrl {
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/*
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* gpio0agrp cover line 0-4
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* gpio0bgrp cover line 5
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*/
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gpio0_default_pins: pinctrl-gpio0 {
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mux {
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function = "gpio0";
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groups = "gpio0agrp", "gpio0bgrp";
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};
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};
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pflash_disabled_pins: pinctrl-pflash-disabled {
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mux {
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function = "gpio0";
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groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp",
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"gpio0kgrp";
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};
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};
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pinctrl-gmii {
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/* This platform use both the ethernet ports */
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mux {
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function = "gmii";
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groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
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};
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};
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};
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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