mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-29 04:09:39 +00:00
drm/i915: Mask USER interrupts on gen6 (until required)
Otherwise we may consume 20% of the CPU just handling IRQs whilst rendering. Ouch. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
parent
b72f3acb71
commit
0f46832fab
5 changed files with 113 additions and 62 deletions
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@ -1007,12 +1007,6 @@ extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
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extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
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extern int i915_vblank_swap(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
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extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
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extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
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u32 mask);
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extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
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u32 mask);
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void
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i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
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@ -64,26 +64,6 @@
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#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
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DRM_I915_VBLANK_PIPE_B)
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void
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ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->gt_irq_mask & mask) != 0) {
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dev_priv->gt_irq_mask &= ~mask;
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
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POSTING_READ(GTIMR);
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}
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}
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void
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ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->gt_irq_mask & mask) != mask) {
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dev_priv->gt_irq_mask |= mask;
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
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POSTING_READ(GTIMR);
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}
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}
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/* For display hotplug interrupt */
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static void
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ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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@ -105,26 +85,6 @@ ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
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}
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}
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void
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i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->irq_mask & mask) != 0) {
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dev_priv->irq_mask &= ~mask;
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I915_WRITE(IMR, dev_priv->irq_mask);
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POSTING_READ(IMR);
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}
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}
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void
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i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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if ((dev_priv->irq_mask & mask) != mask) {
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dev_priv->irq_mask |= mask;
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I915_WRITE(IMR, dev_priv->irq_mask);
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POSTING_READ(IMR);
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}
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}
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static inline u32
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i915_pipestat(int pipe)
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{
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@ -1673,11 +1633,6 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
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I915_WRITE(GTIIR, I915_READ(GTIIR));
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
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if (IS_GEN6(dev)) {
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I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_USER_INTERRUPT);
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I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_USER_INTERRUPT);
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I915_WRITE(GEN6_BLITTER_IMR, ~GEN6_BLITTER_USER_INTERRUPT);
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}
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if (IS_GEN6(dev))
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render_irqs =
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@ -288,6 +288,7 @@
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#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
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#define RING_ACTHD(base) ((base)+0x74)
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#define RING_NOPID(base) ((base)+0x94)
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#define RING_IMR(base) ((base)+0xa8)
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#define TAIL_ADDR 0x001FFFF8
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#define HEAD_WRAP_COUNT 0xFFE00000
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#define HEAD_WRAP_ONE 0x00200000
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@ -485,6 +485,38 @@ pc_render_get_seqno(struct intel_ring_buffer *ring)
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return pc->cpu_page[0];
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}
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static void
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ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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dev_priv->gt_irq_mask &= ~mask;
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
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POSTING_READ(GTIMR);
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}
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static void
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ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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dev_priv->gt_irq_mask |= mask;
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
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POSTING_READ(GTIMR);
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}
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static void
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i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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dev_priv->irq_mask &= ~mask;
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I915_WRITE(IMR, dev_priv->irq_mask);
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POSTING_READ(IMR);
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}
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static void
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i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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dev_priv->irq_mask |= mask;
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I915_WRITE(IMR, dev_priv->irq_mask);
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POSTING_READ(IMR);
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}
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static bool
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render_ring_get_irq(struct intel_ring_buffer *ring)
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{
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@ -499,8 +531,8 @@ render_ring_get_irq(struct intel_ring_buffer *ring)
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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if (HAS_PCH_SPLIT(dev))
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ironlake_enable_graphics_irq(dev_priv,
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GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
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ironlake_enable_irq(dev_priv,
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GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
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else
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i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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@ -520,9 +552,9 @@ render_ring_put_irq(struct intel_ring_buffer *ring)
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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if (HAS_PCH_SPLIT(dev))
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ironlake_disable_graphics_irq(dev_priv,
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GT_USER_INTERRUPT |
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GT_PIPE_NOTIFY);
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ironlake_disable_irq(dev_priv,
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GT_USER_INTERRUPT |
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GT_PIPE_NOTIFY);
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else
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i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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@ -596,7 +628,7 @@ ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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ironlake_enable_graphics_irq(dev_priv, flag);
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ironlake_enable_irq(dev_priv, flag);
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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}
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@ -613,7 +645,46 @@ ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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ironlake_disable_graphics_irq(dev_priv, flag);
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ironlake_disable_irq(dev_priv, flag);
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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}
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}
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static bool
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gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
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{
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struct drm_device *dev = ring->dev;
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if (!dev->irq_enabled)
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return false;
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if (atomic_inc_return(&ring->irq_refcount) == 1) {
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drm_i915_private_t *dev_priv = dev->dev_private;
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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ring->irq_mask &= ~rflag;
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I915_WRITE_IMR(ring, ring->irq_mask);
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ironlake_enable_irq(dev_priv, gflag);
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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}
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return true;
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}
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static void
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gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
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{
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struct drm_device *dev = ring->dev;
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if (atomic_dec_and_test(&ring->irq_refcount)) {
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drm_i915_private_t *dev_priv = dev->dev_private;
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unsigned long irqflags;
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spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
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ring->irq_mask |= rflag;
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I915_WRITE_IMR(ring, ring->irq_mask);
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ironlake_disable_irq(dev_priv, gflag);
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spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
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}
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}
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@ -757,6 +828,7 @@ int intel_init_ring_buffer(struct drm_device *dev,
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INIT_LIST_HEAD(&ring->active_list);
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INIT_LIST_HEAD(&ring->request_list);
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INIT_LIST_HEAD(&ring->gpu_write_list);
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ring->irq_mask = ~0;
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if (I915_NEED_GFX_HWS(dev)) {
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ret = init_status_page(ring);
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@ -1029,16 +1101,36 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
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return 0;
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}
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static bool
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gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
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{
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return gen6_ring_get_irq(ring,
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GT_USER_INTERRUPT,
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GEN6_RENDER_USER_INTERRUPT);
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}
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static void
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gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
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{
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return gen6_ring_put_irq(ring,
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GT_USER_INTERRUPT,
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GEN6_RENDER_USER_INTERRUPT);
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}
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static bool
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gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
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{
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return ring_get_irq(ring, GT_GEN6_BSD_USER_INTERRUPT);
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return gen6_ring_get_irq(ring,
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GT_GEN6_BSD_USER_INTERRUPT,
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GEN6_BSD_USER_INTERRUPT);
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}
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static void
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gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
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{
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ring_put_irq(ring, GT_GEN6_BSD_USER_INTERRUPT);
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return gen6_ring_put_irq(ring,
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GT_GEN6_BSD_USER_INTERRUPT,
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GEN6_BSD_USER_INTERRUPT);
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}
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/* ring buffer for Video Codec for Gen6+ */
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@ -1062,13 +1154,17 @@ static const struct intel_ring_buffer gen6_bsd_ring = {
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static bool
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blt_ring_get_irq(struct intel_ring_buffer *ring)
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{
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return ring_get_irq(ring, GT_BLT_USER_INTERRUPT);
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return gen6_ring_get_irq(ring,
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GT_BLT_USER_INTERRUPT,
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GEN6_BLITTER_USER_INTERRUPT);
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}
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static void
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blt_ring_put_irq(struct intel_ring_buffer *ring)
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{
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ring_put_irq(ring, GT_BLT_USER_INTERRUPT);
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gen6_ring_put_irq(ring,
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GT_BLT_USER_INTERRUPT,
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GEN6_BLITTER_USER_INTERRUPT);
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}
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@ -1192,6 +1288,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
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*ring = render_ring;
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if (INTEL_INFO(dev)->gen >= 6) {
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ring->add_request = gen6_add_request;
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ring->irq_get = gen6_render_ring_get_irq;
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ring->irq_put = gen6_render_ring_put_irq;
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} else if (IS_GEN5(dev)) {
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ring->add_request = pc_render_add_request;
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ring->get_seqno = pc_render_get_seqno;
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@ -28,6 +28,8 @@ struct intel_hw_status_page {
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#define I915_READ_CTL(ring) I915_RING_READ(RING_CTL(ring->mmio_base))
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#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL(ring->mmio_base), val)
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#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR(ring->mmio_base), val)
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#define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID(ring->mmio_base))
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#define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0(ring->mmio_base))
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#define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1(ring->mmio_base))
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@ -52,6 +54,7 @@ struct intel_ring_buffer {
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int effective_size;
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struct intel_hw_status_page status_page;
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u32 irq_mask;
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u32 irq_seqno; /* last seq seem at irq time */
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u32 waiting_seqno;
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u32 sync_seqno[I915_NUM_RINGS-1];
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