From 0f5a869600141a0d5575e3190af01a050c081b07 Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Thu, 6 Mar 2014 09:39:24 +0800 Subject: [PATCH] Corenet: Add QE platform support for Corenet There is QE on platform T104x, add support. Call funcs qe_ic_init and qe_init if CONFIG_QUICC_ENGINE is defined. Signed-off-by: Zhao Qiang [scottwood@freesacle.com: whitespace fix] Signed-off-by: Scott Wood --- arch/powerpc/platforms/85xx/corenet_generic.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c index fbd871e69754..a8877c4e10ad 100644 --- a/arch/powerpc/platforms/85xx/corenet_generic.c +++ b/arch/powerpc/platforms/85xx/corenet_generic.c @@ -26,11 +26,13 @@ #include #include #include +#include #include #include #include #include "smp.h" +#include "mpc85xx.h" void __init corenet_gen_pic_init(void) { @@ -38,6 +40,8 @@ void __init corenet_gen_pic_init(void) unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU | MPIC_NO_RESET; + struct device_node *np; + if (ppc_md.get_irq == mpic_get_coreint_irq) flags |= MPIC_ENABLE_COREINT; @@ -45,6 +49,13 @@ void __init corenet_gen_pic_init(void) BUG_ON(mpic == NULL); mpic_init(mpic); + + np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); + if (np) { + qe_ic_init(np, 0, qe_ic_cascade_low_mpic, + qe_ic_cascade_high_mpic); + of_node_put(np); + } } /* @@ -57,6 +68,8 @@ void __init corenet_gen_setup_arch(void) swiotlb_detect_4g(); pr_info("%s board from Freescale Semiconductor\n", ppc_md.name); + + mpc85xx_qe_init(); } static const struct of_device_id of_device_ids[] = { @@ -81,6 +94,9 @@ static const struct of_device_id of_device_ids[] = { { .compatible = "fsl,qoriq-pcie-v3.0", }, + { + .compatible = "fsl,qe", + }, /* The following two are for the Freescale hypervisor */ { .name = "hypervisor",