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powerpc/8xx: Enhance readability of trap types
This patch makes use of trap types in head_8xx.S Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/e1147287bf6f2fb0693048fe8db0298c7870e419.1618847273.git.christophe.leroy@csgroup.eu
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2 changed files with 47 additions and 31 deletions
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@ -2,13 +2,6 @@
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#ifndef _ASM_POWERPC_INTERRUPT_H
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#define _ASM_POWERPC_INTERRUPT_H
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#include <linux/context_tracking.h>
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#include <linux/hardirq.h>
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#include <asm/cputime.h>
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#include <asm/ftrace.h>
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#include <asm/kprobes.h>
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#include <asm/runlatch.h>
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/* BookE/4xx */
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#define INTERRUPT_CRITICAL_INPUT 0x100
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@ -39,9 +32,11 @@
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/* BookE/BookS/4xx/8xx */
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#define INTERRUPT_DATA_STORAGE 0x300
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#define INTERRUPT_INST_STORAGE 0x400
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#define INTERRUPT_EXTERNAL 0x500
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#define INTERRUPT_ALIGNMENT 0x600
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#define INTERRUPT_PROGRAM 0x700
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#define INTERRUPT_SYSCALL 0xc00
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#define INTERRUPT_TRACE 0xd00
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/* BookE/BookS/44x */
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#define INTERRUPT_FP_UNAVAIL 0x800
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@ -53,6 +48,24 @@
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#define INTERRUPT_PERFMON 0x0
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#endif
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/* 8xx */
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#define INTERRUPT_SOFT_EMU_8xx 0x1000
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#define INTERRUPT_INST_TLB_MISS_8xx 0x1100
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#define INTERRUPT_DATA_TLB_MISS_8xx 0x1200
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#define INTERRUPT_INST_TLB_ERROR_8xx 0x1300
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#define INTERRUPT_DATA_TLB_ERROR_8xx 0x1400
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#define INTERRUPT_DATA_BREAKPOINT_8xx 0x1c00
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#define INTERRUPT_INST_BREAKPOINT_8xx 0x1d00
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#ifndef __ASSEMBLY__
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#include <linux/context_tracking.h>
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#include <linux/hardirq.h>
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#include <asm/cputime.h>
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#include <asm/ftrace.h>
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#include <asm/kprobes.h>
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#include <asm/runlatch.h>
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static inline void nap_adjust_return(struct pt_regs *regs)
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{
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#ifdef CONFIG_PPC_970_NAP
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@ -514,4 +527,6 @@ static inline void interrupt_cond_local_irq_enable(struct pt_regs *regs)
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local_irq_enable();
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_INTERRUPT_H */
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@ -29,6 +29,7 @@
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#include <asm/ptrace.h>
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#include <asm/export.h>
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#include <asm/code-patching-asm.h>
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#include <asm/interrupt.h>
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/*
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* Value for the bits that have fixed value in RPN entries.
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@ -118,49 +119,49 @@ instruction_counter:
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#endif
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/* System reset */
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EXCEPTION(0x100, Reset, system_reset_exception)
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EXCEPTION(INTERRUPT_SYSTEM_RESET, Reset, system_reset_exception)
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/* Machine check */
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START_EXCEPTION(0x200, MachineCheck)
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EXCEPTION_PROLOG 0x200 MachineCheck handle_dar_dsisr=1
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START_EXCEPTION(INTERRUPT_MACHINE_CHECK, MachineCheck)
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EXCEPTION_PROLOG INTERRUPT_MACHINE_CHECK MachineCheck handle_dar_dsisr=1
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prepare_transfer_to_handler
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bl machine_check_exception
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b interrupt_return
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/* External interrupt */
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EXCEPTION(0x500, HardwareInterrupt, do_IRQ)
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EXCEPTION(INTERRUPT_EXTERNAL, HardwareInterrupt, do_IRQ)
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/* Alignment exception */
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START_EXCEPTION(0x600, Alignment)
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EXCEPTION_PROLOG 0x600 Alignment handle_dar_dsisr=1
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START_EXCEPTION(INTERRUPT_ALIGNMENT, Alignment)
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EXCEPTION_PROLOG INTERRUPT_ALIGNMENT Alignment handle_dar_dsisr=1
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prepare_transfer_to_handler
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bl alignment_exception
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REST_NVGPRS(r1)
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b interrupt_return
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/* Program check exception */
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START_EXCEPTION(0x700, ProgramCheck)
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EXCEPTION_PROLOG 0x700 ProgramCheck
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START_EXCEPTION(INTERRUPT_PROGRAM, ProgramCheck)
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EXCEPTION_PROLOG INTERRUPT_PROGRAM ProgramCheck
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prepare_transfer_to_handler
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bl program_check_exception
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REST_NVGPRS(r1)
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b interrupt_return
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/* Decrementer */
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EXCEPTION(0x900, Decrementer, timer_interrupt)
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EXCEPTION(INTERRUPT_DECREMENTER, Decrementer, timer_interrupt)
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/* System call */
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START_EXCEPTION(0xc00, SystemCall)
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SYSCALL_ENTRY 0xc00
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START_EXCEPTION(INTERRUPT_SYSCALL, SystemCall)
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SYSCALL_ENTRY INTERRUPT_SYSCALL
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/* Single step - not used on 601 */
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EXCEPTION(0xd00, SingleStep, single_step_exception)
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EXCEPTION(INTERRUPT_TRACE, SingleStep, single_step_exception)
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/* On the MPC8xx, this is a software emulation interrupt. It occurs
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* for all unimplemented and illegal instructions.
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*/
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START_EXCEPTION(0x1000, SoftEmu)
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EXCEPTION_PROLOG 0x1000 SoftEmu
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START_EXCEPTION(INTERRUPT_SOFT_EMU_8xx, SoftEmu)
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EXCEPTION_PROLOG INTERRUPT_SOFT_EMU_8xx SoftEmu
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prepare_transfer_to_handler
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bl emulation_assist_interrupt
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REST_NVGPRS(r1)
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@ -187,7 +188,7 @@ instruction_counter:
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#define INVALIDATE_ADJACENT_PAGES_CPU15(addr, tmp)
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#endif
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START_EXCEPTION(0x1100, InstructionTLBMiss)
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START_EXCEPTION(INTERRUPT_INST_TLB_MISS_8xx, InstructionTLBMiss)
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mtspr SPRN_SPRG_SCRATCH2, r10
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mtspr SPRN_M_TW, r11
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@ -243,7 +244,7 @@ instruction_counter:
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rfi
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#endif
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START_EXCEPTION(0x1200, DataStoreTLBMiss)
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START_EXCEPTION(INTERRUPT_DATA_TLB_MISS_8xx, DataStoreTLBMiss)
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mtspr SPRN_SPRG_SCRATCH2, r10
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mtspr SPRN_M_TW, r11
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mfcr r11
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@ -306,9 +307,9 @@ instruction_counter:
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* to many reasons, such as executing guarded memory or illegal instruction
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* addresses. There is nothing to do but handle a big time error fault.
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*/
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START_EXCEPTION(0x1300, InstructionTLBError)
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START_EXCEPTION(INTERRUPT_INST_TLB_ERROR_8xx, InstructionTLBError)
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/* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
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EXCEPTION_PROLOG 0x400 InstructionTLBError
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EXCEPTION_PROLOG INTERRUPT_INST_STORAGE InstructionTLBError
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andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
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andis. r10,r9,SRR1_ISI_NOPT@h
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beq+ .Litlbie
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@ -324,7 +325,7 @@ instruction_counter:
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* many reasons, including a dirty update to a pte. We bail out to
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* a higher level function that can handle it.
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*/
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START_EXCEPTION(0x1400, DataTLBError)
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START_EXCEPTION(INTERRUPT_DATA_TLB_ERROR_8xx, DataTLBError)
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EXCEPTION_PROLOG_0 handle_dar_dsisr=1
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mfspr r11, SPRN_DAR
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cmpwi cr1, r11, RPN_PATTERN
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@ -332,7 +333,7 @@ instruction_counter:
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DARFixed:/* Return from dcbx instruction bug workaround */
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EXCEPTION_PROLOG_1
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/* 0x300 is DataAccess exception, needed by bad_page_fault() */
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EXCEPTION_PROLOG_2 0x300 DataTLBError handle_dar_dsisr=1
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EXCEPTION_PROLOG_2 INTERRUPT_DATA_STORAGE DataTLBError handle_dar_dsisr=1
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lwz r4, _DAR(r11)
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lwz r5, _DSISR(r11)
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andis. r10,r5,DSISR_NOHPTE@h
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@ -351,7 +352,7 @@ DARFixed:/* Return from dcbx instruction bug workaround */
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* support of breakpoints and such. Someday I will get around to
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* using them.
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*/
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START_EXCEPTION(0x1c00, DataBreakpoint)
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START_EXCEPTION(INTERRUPT_DATA_BREAKPOINT_8xx, DataBreakpoint)
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EXCEPTION_PROLOG_0 handle_dar_dsisr=1
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mfspr r11, SPRN_SRR0
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cmplwi cr1, r11, (.Ldtlbie - PAGE_OFFSET)@l
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@ -364,7 +365,7 @@ DARFixed:/* Return from dcbx instruction bug workaround */
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rfi
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1: EXCEPTION_PROLOG_1
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EXCEPTION_PROLOG_2 0x1c00 DataBreakpoint handle_dar_dsisr=1
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EXCEPTION_PROLOG_2 INTERRUPT_DATA_BREAKPOINT_8xx DataBreakpoint handle_dar_dsisr=1
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mfspr r4,SPRN_BAR
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stw r4,_DAR(r11)
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prepare_transfer_to_handler
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b interrupt_return
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#ifdef CONFIG_PERF_EVENTS
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START_EXCEPTION(0x1d00, InstructionBreakpoint)
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START_EXCEPTION(INTERRUPT_INST_BREAKPOINT_8xx, InstructionBreakpoint)
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mtspr SPRN_SPRG_SCRATCH0, r10
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lwz r10, (instruction_counter - PAGE_OFFSET)@l(0)
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addi r10, r10, -1
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@ -384,7 +385,7 @@ DARFixed:/* Return from dcbx instruction bug workaround */
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mfspr r10, SPRN_SPRG_SCRATCH0
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rfi
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#else
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EXCEPTION(0x1d00, Trap_1d, unknown_exception)
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EXCEPTION(INTERRUPT_INST_BREAKPOINT_8xx, Trap_1d, unknown_exception)
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#endif
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EXCEPTION(0x1e00, Trap_1e, unknown_exception)
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EXCEPTION(0x1f00, Trap_1f, unknown_exception)
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