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drm/amdgpu: allow direct submission of clears
For handling PD/PT clears directly in the fault handler. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
acb476f541
commit
0f6064d6af
1 changed files with 11 additions and 6 deletions
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@ -695,6 +695,7 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm)
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* @adev: amdgpu_device pointer
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* @adev: amdgpu_device pointer
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* @vm: VM to clear BO from
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* @vm: VM to clear BO from
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* @bo: BO to clear
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* @bo: BO to clear
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* @direct: use a direct update
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*
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*
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* Root PD needs to be reserved when calling this.
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* Root PD needs to be reserved when calling this.
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*
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*
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@ -703,7 +704,8 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm)
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*/
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*/
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static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
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static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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struct amdgpu_vm *vm,
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struct amdgpu_bo *bo)
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struct amdgpu_bo *bo,
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bool direct)
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{
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{
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struct ttm_operation_ctx ctx = { true, false };
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struct ttm_operation_ctx ctx = { true, false };
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unsigned level = adev->vm_manager.root_level;
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unsigned level = adev->vm_manager.root_level;
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@ -762,6 +764,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
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memset(¶ms, 0, sizeof(params));
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memset(¶ms, 0, sizeof(params));
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params.adev = adev;
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params.adev = adev;
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params.vm = vm;
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params.vm = vm;
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params.direct = direct;
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r = vm->update_funcs->prepare(¶ms, AMDGPU_FENCE_OWNER_KFD, NULL);
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r = vm->update_funcs->prepare(¶ms, AMDGPU_FENCE_OWNER_KFD, NULL);
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if (r)
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if (r)
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@ -852,7 +855,8 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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*/
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*/
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static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
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static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
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struct amdgpu_vm *vm,
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struct amdgpu_vm *vm,
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struct amdgpu_vm_pt_cursor *cursor)
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struct amdgpu_vm_pt_cursor *cursor,
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bool direct)
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{
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{
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struct amdgpu_vm_pt *entry = cursor->entry;
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struct amdgpu_vm_pt *entry = cursor->entry;
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struct amdgpu_bo_param bp;
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struct amdgpu_bo_param bp;
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@ -885,7 +889,7 @@ static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
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pt->parent = amdgpu_bo_ref(cursor->parent->base.bo);
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pt->parent = amdgpu_bo_ref(cursor->parent->base.bo);
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amdgpu_vm_bo_base_init(&entry->base, vm, pt);
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amdgpu_vm_bo_base_init(&entry->base, vm, pt);
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r = amdgpu_vm_clear_bo(adev, vm, pt);
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r = amdgpu_vm_clear_bo(adev, vm, pt, direct);
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if (r)
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if (r)
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goto error_free_pt;
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goto error_free_pt;
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@ -1401,7 +1405,8 @@ static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
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uint64_t incr, entry_end, pe_start;
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uint64_t incr, entry_end, pe_start;
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struct amdgpu_bo *pt;
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struct amdgpu_bo *pt;
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r = amdgpu_vm_alloc_pts(params->adev, params->vm, &cursor);
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r = amdgpu_vm_alloc_pts(params->adev, params->vm, &cursor,
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params->direct);
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if (r)
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if (r)
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return r;
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return r;
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@ -2726,7 +2731,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
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amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
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r = amdgpu_vm_clear_bo(adev, vm, root);
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r = amdgpu_vm_clear_bo(adev, vm, root, false);
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if (r)
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if (r)
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goto error_unreserve;
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goto error_unreserve;
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@ -2849,7 +2854,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, uns
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*/
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*/
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if (pte_support_ats != vm->pte_support_ats) {
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if (pte_support_ats != vm->pte_support_ats) {
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vm->pte_support_ats = pte_support_ats;
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vm->pte_support_ats = pte_support_ats;
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r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo);
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r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, false);
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if (r)
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if (r)
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goto free_idr;
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goto free_idr;
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}
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}
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