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Merge branch 'topic/bjorn-trivial' into next
* topic/bjorn-trivial: PCI: remove useless pcix_set_mmrbc() dev->bus check PCI: acpiphp: check whether _ADR evaluation succeeded PCI: shpchp: remove dead code PCI: fix P2P bridge I/O port window sign extension PCI: fix upstream P2P bridge checks when enabling OBFF and LTR PCI: use __weak consistently PCI: cleanup assign_requested_resources_sorted() kernel-doc warning sparc/PCI: remove unused pcibios_assign_resource() definition
This commit is contained in:
commit
0f6662a49b
7 changed files with 28 additions and 30 deletions
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@ -884,11 +884,6 @@ void __init sun4m_pci_init_IRQ(void)
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sparc_config.load_profile_irq = pcic_load_profile_irq;
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}
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int pcibios_assign_resource(struct pci_dev *pdev, int resource)
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{
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return -ENXIO;
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}
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/*
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* This probably belongs here rather than ioport.c because
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* we do not want this crud linked into SBus kernels.
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@ -132,6 +132,15 @@ register_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
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if (!acpi_pci_check_ejectable(pbus, handle) && !is_dock_device(handle))
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return AE_OK;
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status = acpi_evaluate_integer(handle, "_ADR", NULL, &adr);
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if (ACPI_FAILURE(status)) {
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warn("can't evaluate _ADR (%#x)\n", status);
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return AE_OK;
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}
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device = (adr >> 16) & 0xffff;
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function = adr & 0xffff;
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pdev = pbus->self;
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if (pdev && pci_is_pcie(pdev)) {
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tmp = acpi_find_root_bridge_handle(pdev);
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@ -144,10 +153,6 @@ register_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
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}
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}
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acpi_evaluate_integer(handle, "_ADR", NULL, &adr);
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device = (adr >> 16) & 0xffff;
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function = adr & 0xffff;
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newfunc = kzalloc(sizeof(struct acpiphp_func), GFP_KERNEL);
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if (!newfunc)
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return AE_NO_MEMORY;
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@ -262,9 +262,6 @@ static int board_added(struct slot *p_slot)
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}
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if ((ctrl->pci_dev->vendor == 0x8086) && (ctrl->pci_dev->device == 0x0332)) {
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if (slots_not_empty)
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return WRONG_BUS_FREQUENCY;
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if ((rc = p_slot->hpc_ops->set_bus_speed_mode(p_slot, PCI_SPEED_33MHz))) {
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ctrl_err(ctrl, "%s: Issue of set bus speed mode command"
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" failed\n", __func__);
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@ -1112,7 +1112,7 @@ static struct bin_attribute pcie_config_attr = {
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.write = pci_write_config,
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};
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int __attribute__ ((weak)) pcibios_add_platform_entries(struct pci_dev *dev)
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int __weak pcibios_add_platform_entries(struct pci_dev *dev)
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{
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return 0;
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}
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@ -1311,7 +1311,7 @@ void pcim_pin_device(struct pci_dev *pdev)
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* is the default implementation. Architecture implementations can
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* override this.
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*/
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void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
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void __weak pcibios_disable_device (struct pci_dev *dev) {}
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static void do_pci_disable_device(struct pci_dev *dev)
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{
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@ -1375,8 +1375,8 @@ pci_disable_device(struct pci_dev *dev)
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* Sets the PCIe reset state for the device. This is the default
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* implementation. Architecture implementations can override this.
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*/
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int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
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enum pcie_reset_state state)
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int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
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enum pcie_reset_state state)
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{
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return -EINVAL;
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}
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@ -2063,7 +2063,7 @@ int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
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return -ENOTSUPP; /* no OBFF support at all */
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/* Make sure the topology supports OBFF as well */
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if (dev->bus) {
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if (dev->bus->self) {
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ret = pci_enable_obff(dev->bus->self, type);
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if (ret)
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return ret;
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@ -2166,7 +2166,7 @@ int pci_enable_ltr(struct pci_dev *dev)
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return -EINVAL;
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/* Enable upstream ports first */
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if (dev->bus) {
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if (dev->bus->self) {
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ret = pci_enable_ltr(dev->bus->self);
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if (ret)
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return ret;
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@ -3419,8 +3419,7 @@ int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
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o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
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if (o != v) {
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if (v > o && dev->bus &&
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(dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
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if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
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return -EIO;
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cmd &= ~PCI_X_CMD_MAX_READ;
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@ -3875,7 +3874,7 @@ static void __devinit pci_no_domains(void)
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* greater than 0xff). This is the default implementation. Architecture
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* implementations can override this.
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*/
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int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
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int __weak pci_ext_cfg_avail(struct pci_dev *dev)
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{
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return 1;
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}
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@ -318,10 +318,11 @@ static void __devinit pci_read_bridge_io(struct pci_bus *child)
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if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
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u16 io_base_hi, io_limit_hi;
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pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
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pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
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base |= (io_base_hi << 16);
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limit |= (io_limit_hi << 16);
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base |= ((unsigned long) io_base_hi << 16);
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limit |= ((unsigned long) io_limit_hi << 16);
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}
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if (base && base <= limit) {
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@ -349,8 +350,8 @@ static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
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res = child->resource[1];
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pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
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pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
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base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
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limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
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base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
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limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
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if (base && base <= limit) {
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res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
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region.start = base;
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@ -371,11 +372,12 @@ static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
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res = child->resource[2];
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pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
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pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
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base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
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limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
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base = ((unsigned long) mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
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limit = ((unsigned long) mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
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if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
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u32 mem_base_hi, mem_limit_hi;
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pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
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pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
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@ -386,8 +388,8 @@ static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
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*/
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if (mem_base_hi <= mem_limit_hi) {
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#if BITS_PER_LONG == 64
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base |= ((long) mem_base_hi) << 32;
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limit |= ((long) mem_limit_hi) << 32;
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base |= ((unsigned long) mem_base_hi) << 32;
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limit |= ((unsigned long) mem_limit_hi) << 32;
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#else
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if (mem_base_hi || mem_limit_hi) {
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dev_err(&dev->dev, "can't handle 64-bit "
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@ -265,7 +265,7 @@ static void reassign_resources_sorted(struct list_head *realloc_head,
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* assign_requested_resources_sorted() - satisfy resource requests
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*
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* @head : head of the list tracking requests for resources
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* @failed_list : head of the list tracking requests that could
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* @fail_head : head of the list tracking requests that could
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* not be allocated
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*
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* Satisfy resource requests of each element in the list. Add
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