mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-07 03:18:31 +00:00
iommu/vt-d: Add definitions for PFSID
When SRIOV VF device IOTLB is invalidated, we need to provide the PF source ID such that IOMMU hardware can gauge the depth of invalidation queue which is shared among VFs. This is needed when device invalidation throttle (DIT) capability is supported. This patch adds bit definitions for checking and tracking PFSID. Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: stable@vger.kernel.org Cc: "Ashok Raj" <ashok.raj@intel.com> Cc: "Lu Baolu" <baolu.lu@linux.intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
parent
021c91791a
commit
0f725561e1
2 changed files with 4 additions and 0 deletions
|
@ -422,6 +422,7 @@ struct device_domain_info {
|
||||||
struct list_head global; /* link to global list */
|
struct list_head global; /* link to global list */
|
||||||
u8 bus; /* PCI bus number */
|
u8 bus; /* PCI bus number */
|
||||||
u8 devfn; /* PCI devfn number */
|
u8 devfn; /* PCI devfn number */
|
||||||
|
u16 pfsid; /* SRIOV physical function source ID */
|
||||||
u8 pasid_supported:3;
|
u8 pasid_supported:3;
|
||||||
u8 pasid_enabled:1;
|
u8 pasid_enabled:1;
|
||||||
u8 pri_supported:1;
|
u8 pri_supported:1;
|
||||||
|
|
|
@ -114,6 +114,7 @@
|
||||||
* Extended Capability Register
|
* Extended Capability Register
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#define ecap_dit(e) ((e >> 41) & 0x1)
|
||||||
#define ecap_pasid(e) ((e >> 40) & 0x1)
|
#define ecap_pasid(e) ((e >> 40) & 0x1)
|
||||||
#define ecap_pss(e) ((e >> 35) & 0x1f)
|
#define ecap_pss(e) ((e >> 35) & 0x1f)
|
||||||
#define ecap_eafs(e) ((e >> 34) & 0x1)
|
#define ecap_eafs(e) ((e >> 34) & 0x1)
|
||||||
|
@ -283,6 +284,7 @@ enum {
|
||||||
#define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
|
#define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
|
||||||
#define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
|
#define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
|
||||||
#define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
|
#define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
|
||||||
|
#define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff) << 52))
|
||||||
#define QI_DEV_IOTLB_SIZE 1
|
#define QI_DEV_IOTLB_SIZE 1
|
||||||
#define QI_DEV_IOTLB_MAX_INVS 32
|
#define QI_DEV_IOTLB_MAX_INVS 32
|
||||||
|
|
||||||
|
@ -307,6 +309,7 @@ enum {
|
||||||
#define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
|
#define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
|
||||||
#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
|
#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
|
||||||
#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
|
#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
|
||||||
|
#define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff) << 52))
|
||||||
#define QI_DEV_EIOTLB_MAX_INVS 32
|
#define QI_DEV_EIOTLB_MAX_INVS 32
|
||||||
|
|
||||||
#define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)
|
#define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)
|
||||||
|
|
Loading…
Reference in a new issue