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staging: rtl8188eu: remove PWR_BASEADDR_* macro definitions and "base" member of wl_pwr_cfg structure
These macros and "base" member of wl_pwr_cfg structure are used only to produce debug output. Signed-off-by: Ivan Safonov <insafonov@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
0e54dbd4c7
commit
0f94b0afcd
3 changed files with 63 additions and 114 deletions
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@ -39,11 +39,10 @@ u8 rtl88eu_pwrseqcmdparsing(struct adapter *padapter, u8 cut_vers,
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RT_TRACE(_module_hal_init_c_, _drv_info_,
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("rtl88eu_pwrseqcmdparsing: offset(%#x) cut_msk(%#x)"
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" base(%#x) cmd(%#x)"
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" cmd(%#x)"
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"msk(%#x) value(%#x)\n",
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GET_PWR_CFG_OFFSET(pwrcfgcmd),
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GET_PWR_CFG_CUT_MASK(pwrcfgcmd),
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GET_PWR_CFG_BASE(pwrcfgcmd),
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GET_PWR_CFG_CMD(pwrcfgcmd),
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GET_PWR_CFG_MASK(pwrcfgcmd),
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GET_PWR_CFG_VALUE(pwrcfgcmd)));
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@ -60,213 +60,172 @@
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#define RTL8188E_TRANS_CARDEMU_TO_ACT \
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/* format
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* { offset, cut_msk, interface_msk, base|cmd, msk, value
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* { offset, cut_msk, cmd, msk, value
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* },
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* comment here
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*/ \
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{0x0006, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
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{0x0006, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
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/* wait till 0x04[17] = 1 power ready*/ \
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{0x0002, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \
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{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \
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/* 0x02[1:0] = 0 reset BB*/ \
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{0x0026, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
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{0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
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/*0x24[23] = 2b'01 schmit trigger */ \
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{0x0005, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \
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/* 0x04[15] = 0 disable HWPDN (control by DRV)*/ \
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{0x0005, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \
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/*0x04[12:11] = 2b'00 disable WL suspend*/ \
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{0x0005, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
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/*0x04[8] = 1 polling until return 0*/ \
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{0x0005, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(0), 0}, \
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/*wait till 0x04[8] = 0*/ \
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{0x0023, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
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{0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
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/*LDO normal mode*/
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#define RTL8188E_TRANS_ACT_TO_CARDEMU \
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/* format
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* { offset, cut_msk, interface_msk, base|cmd, msk, value
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* { offset, cut_msk, cmd, msk, value
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* },
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* comments here
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*/ \
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{0x001F, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
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{0x001F, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \
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/*0x1F[7:0] = 0 turn off RF*/ \
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{0x0023, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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{0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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/*LDO Sleep mode*/ \
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{0x0005, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
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/*0x04[9] = 1 turn off MAC by HW state machine*/ \
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{0x0005, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), 0}, \
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/*wait till 0x04[9] = 0 polling until return 0 to disable*/
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#define RTL8188E_TRANS_CARDEMU_TO_SUS \
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/* format
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* { offset, cut_msk, interface_msk, base|cmd, msk,
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
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/* 0x04[12:11] = 2b'01enable WL suspend */ \
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{0x0007, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, 0xFF, BIT(7)}, \
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{0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, BIT(7)}, \
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/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
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{0x0041, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, BIT(4), 0}, \
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{0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
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/*Clear SIC_EN register 0x40[12] = 1'b0 */ \
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{0xfe10, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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{0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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/*Set USB suspend enable local register 0xfe10[4]=1 */
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#define RTL8188E_TRANS_SUS_TO_CARDEMU \
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/* format
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* { offset, cut_msk, interface_msk, base|cmd, msk,
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0005, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \
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/*0x04[12:11] = 2b'01enable WL suspend*/
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#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
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/* format
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* { offset, cut_msk, interface_msk, base|cmd, msk,
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0026, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
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{0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
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/*0x24[23] = 2b'01 schmit trigger */ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
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/*0x04[12:11] = 2b'01 enable WL suspend*/ \
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{0x0007, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, 0xFF, 0}, \
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{0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \
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/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
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{0x0041, PWR_CUT_ALL_MSK, PWR_BASEADDR_MAC, \
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PWR_CMD_WRITE, BIT(4), 0}, \
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{0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
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/*Clear SIC_EN register 0x40[12] = 1'b0 */ \
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{0xfe10, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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{0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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/*Set USB suspend enable local register 0xfe10[4]=1 */
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#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
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/* format
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* { offset, cut_msk, interface_msk, base|cmd, msk,
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0005, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \
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/*0x04[12:11] = 2b'01enable WL suspend*/
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#define RTL8188E_TRANS_CARDEMU_TO_PDN \
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/* format
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* { offset, cut_msk, interface_msk, base|cmd, msk,
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0006, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
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{0x0006, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \
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/* 0x04[16] = 0*/ \
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{0x0005, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
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/* 0x04[15] = 1*/
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#define RTL8188E_TRANS_PDN_TO_CARDEMU \
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/* format
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* { offset, cut_msk, interface_msk, base|cmd, msk,
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0005, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \
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/* 0x04[15] = 0*/
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/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
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#define RTL8188E_TRANS_ACT_TO_LPS \
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/* format
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* { offset, cut_msk, interface_msk, base|cmd, msk,
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0522, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
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{0x05F8, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
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{0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
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{0x05F8, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x05F9, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
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{0x05F9, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x05FA, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
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{0x05FA, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x05FB, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
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{0x05FB, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x0002, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
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{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \
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/*CCK and OFDM are disabled,and clock are gated*/ \
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{0x0002, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, \
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PWRSEQ_DELAY_US},/*Delay 1us*/ \
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{0x0100, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
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{0x0101, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/\
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{0x0553, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, \
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{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
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/*Delay 1us*/ \
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{0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x3F}, \
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/*Reset MAC TRX*/ \
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{0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), 0}, \
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/*check if removed later*/\
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{0x0553, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(5), BIT(5)}, \
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/*Respond TxOK to scheduler*/
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#define RTL8188E_TRANS_LPS_TO_ACT \
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/* format
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* { offset, cut_msk, interface_msk, base|cmd, msk,
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0xFE58, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
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{0x0002, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
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{0x0008, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
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{0xFE58, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x84}, \
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/*USB RPWM*/ \
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{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
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/*Delay*/ \
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{0x0008, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
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/* 0x08[4] = 0 switch TSF to 40M */ \
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{0x0109, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
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{0x0109, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(7), 0}, \
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/* Polling 0x109[7]=0 TSF in 40M */ \
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{0x0029, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, \
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{0x0029, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, \
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/* 0x29[7:6] = 2b'00 enable BB clock */ \
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{0x0101, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
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{0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
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/* 0x101[1] = 1 */ \
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{0x0100, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
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{0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0xFF}, \
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/* 0x100[7:0] = 0xFF enable WMAC TRX */ \
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{0x0002, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
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PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
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/* 0x02[1:0] = 2b'11 enable BB macro */ \
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{0x0522, PWR_CUT_ALL_MSK, \
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PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
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{0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
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#define RTL8188E_TRANS_END \
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/* format
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* { offset, cut_msk, interface_msk, base|cmd, msk,
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0xFFFF, PWR_CUT_ALL_MSK, 0, \
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PWR_CMD_END, 0, 0},
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{0xFFFF, PWR_CUT_ALL_MSK, PWR_CMD_END, 0, 0},
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extern struct wl_pwr_cfg rtl8188E_power_on_flow
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@ -29,13 +29,6 @@
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#define PWR_CMD_DELAY 0x03
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#define PWR_CMD_END 0x04
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/* The value of base: 4 bits */
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/* define the base address of each block */
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#define PWR_BASEADDR_MAC 0x00
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#define PWR_BASEADDR_USB 0x01
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#define PWR_BASEADDR_PCIE 0x02
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#define PWR_BASEADDR_SDIO 0x03
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/* The value of cut_msk: 8 bits */
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#define PWR_CUT_TESTCHIP_MSK BIT(0)
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#define PWR_CUT_A_MSK BIT(1)
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@ -56,7 +49,6 @@ enum pwrseq_cmd_delat_unit {
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struct wl_pwr_cfg {
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u16 offset;
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u8 cut_msk;
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u8 base:4;
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u8 cmd:4;
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u8 msk;
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u8 value;
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@ -64,7 +56,6 @@ struct wl_pwr_cfg {
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#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
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#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
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#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
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#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
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#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
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#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
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Reference in a new issue