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drm/i915/display/cnl+: Handle fused off DSC
DSC could be fused off, so not all GEN10+ platforms will support it. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Martin Peres <martin.peres@linux.intel.com> Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191026001323.216052-5-jose.souza@intel.com
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5 changed files with 10 additions and 0 deletions
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@ -1888,6 +1888,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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if (!INTEL_INFO(dev_priv)->display.has_dsc)
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return false;
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/* On TGL, DSC is supported on all Pipes */
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if (INTEL_GEN(dev_priv) >= 12)
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return true;
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@ -737,6 +737,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
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GEN9_FEATURES, \
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GEN(10), \
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.ddb_size = 1024, \
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.display.has_dsc = 1, \
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.has_coherent_ggtt = false, \
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GLK_COLORS
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@ -7755,6 +7755,7 @@ enum {
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#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
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#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
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#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
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#define CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
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#define SKL_DSSM _MMIO(0x51004)
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#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31)
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@ -990,6 +990,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
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if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
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info->display.has_csr = 0;
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if (INTEL_GEN(dev_priv) >= 10 &&
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(dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
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info->display.has_dsc = 0;
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}
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/* Initialize slice/subslice/EU info */
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@ -137,6 +137,7 @@ enum intel_ppgtt_type {
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func(has_ddi); \
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func(has_dp_mst); \
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func(has_dsb); \
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func(has_dsc); \
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func(has_fbc); \
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func(has_gmch); \
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func(has_hdcp); \
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