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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin

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* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (32 commits)
  Blackfin: gpio: add a debounce stub
  Blackfin: update defconfigs
  Blackfin: remove CONFIG_MEM_GENERIC_BOARD
  Blackfin: dpmc: punt unnecessary RTC_ISTAT clearing
  Blackfin: unify rotary encoder bitmasks
  Blackfin: unify SDH/RSI bitmasks
  Blackfin: BF54x: tweak DMAC MMR naming to match other ports
  Blackfin: TWI: clean up the MMR names
  Blackfin: add EVT_OVERRIDE/IPRIO core MMR helpers
  Blackfin: add support for dynamic ftrace
  Blackfin: add support for LZO compressed kernels
  Blackfin: portmux: fix peripheral map overflow when requesting pins
  Blackfin: document SPI CS limitations with CPHA=0
  Blackfin: remove useless and outdated documentation
  Blackfin: BF51x/BF52x: support GPIO Hysteresis/Schmitt Trigger options
  Blackfin: gpio/portmux: clean up whitespace corruption
  Blackfin: make sure mmiowb inserts a write barrier with SSYNC
  Blackfin: fix DMA/cache bug when resuming from suspend to RAM
  Blackfin: BF51x: fix handling of PH8 (the "internal" SPI0SEL4 pin)
  Blackfin: add a GPIO_DEFAULT_BOOT_SPI_CS
  ...
This commit is contained in:
Linus Torvalds 2010-08-09 21:01:11 -07:00
commit 0fc2f13722
87 changed files with 2481 additions and 2094 deletions
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11
Documentation/blackfin/00-INDEX
View file

@ -1,11 +1,8 @@
00-INDEX
- This file
cachefeatures.txt
- Supported cache features.
Filesystems
- Requirements for mounting the root file system.
bfin-gpio-note.txt
bfin-gpio-notes.txt
- Notes in developing/using bfin-gpio driver.
bfin-spi-notes.txt
- Notes for using bfin spi bus driver.

169
Documentation/blackfin/Filesystems
View file

@ -1,169 +0,0 @@
/*
* File: Documentation/blackfin/Filesystems
* Based on:
* Author:
*
* Created:
* Description: This file contains the simple DMA Implementation for Blackfin
*
* Rev: $Id: Filesystems 2384 2006-11-01 04:12:43Z magicyang $
*
* Modified:
* Copyright 2004-2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
*/
How to mount the root file system in uClinux/Blackfin
-----------------------------------------------------
1 Mounting EXT3 File system.
------------------------
Creating an EXT3 File system for uClinux/Blackfin:
Please follow the steps to form the EXT3 File system and mount the same as root
file system.
a Make an ext3 file system as large as you want the final root file
system.
mkfs.ext3 /dev/ram0 <your-rootfs-size-in-1k-blocks>
b Mount this Empty file system on a free directory as:
mount -t ext3 /dev/ram0 ./test
where ./test is the empty directory.
c Copy your root fs directory that you have so carefully made over.
cp -af /tmp/my_final_rootfs_files/* ./test
(For ex: cp -af uClinux-dist/romfs/* ./test)
d If you have done everything right till now you should be able to see
the required "root" dir's (that's etc, root, bin, lib, sbin...)
e Now unmount the file system
umount ./test
f Create the root file system image.
dd if=/dev/ram0 bs=1k count=<your-rootfs-size-in-1k-blocks> \
> ext3fs.img
Now you have to tell the kernel that will be mounting this file system as
rootfs.
So do a make menuconfig under kernel and select the Ext3 journaling file system
support under File system --> submenu.
2. Mounting EXT2 File system.
-------------------------
By default the ext2 file system image will be created if you invoke make from
the top uClinux-dist directory.
3. Mounting CRAMFS File System
----------------------------
To create a CRAMFS file system image execute the command
mkfs.cramfs ./test cramfs.img
where ./test is the target directory.
4. Mounting ROMFS File System
--------------------------
To create a ROMFS file system image execute the command
genromfs -v -V "ROMdisk" -f romfs.img -d ./test
where ./test is the target directory
5. Mounting the JFFS2 Filesystem
-----------------------------
To create a compressed JFFS filesystem (JFFS2), please execute the command
mkfs.jffs2 -d ./test -o jffs2.img
where ./test is the target directory.
However, please make sure the following is in your kernel config.
/*
* RAM/ROM/Flash chip drivers
*/
#define CONFIG_MTD_CFI 1
#define CONFIG_MTD_ROM 1
/*
* Mapping drivers for chip access
*/
#define CONFIG_MTD_COMPLEX_MAPPINGS 1
#define CONFIG_MTD_BF533 1
#undef CONFIG_MTD_UCLINUX
Through the u-boot boot loader, use the jffs2.img in the corresponding
partition made in linux-2.6.x/drivers/mtd/maps/bf533_flash.c.
NOTE - Currently the Flash driver is available only for EZKIT. Watch out for a
STAMP driver soon.
6. Mounting the NFS File system
-----------------------------
For mounting the NFS please do the following in the kernel config.
In Networking Support --> Networking options --> TCP/IP networking -->
IP: kernel level autoconfiguration
Enable BOOTP Support.
In Kernel hacking --> Compiled-in kernel boot parameter add the following
root=/dev/nfs rw ip=bootp
In File system --> Network File system, Enable
NFS file system support --> NFSv3 client support
Root File system on NFS
in uClibc menuconfig, do the following
In Networking Support
enable Remote Procedure Call (RPC) support
Full RPC Support
On the Host side, ensure that /etc/dhcpd.conf looks something like this
ddns-update-style ad-hoc;
allow bootp;
subnet 10.100.4.0 netmask 255.255.255.0 {
default-lease-time 122209600;
max-lease-time 31557600;
group {
host bf533 {
hardware ethernet 00:CF:52:49:C3:01;
fixed-address 10.100.4.50;
option root-path "/home/nfsmount";
}
}
ensure that /etc/exports looks something like this
/home/nfsmount *(rw,no_root_squash,no_all_squash)
run the following commands as root (may differ depending on your
distribution) :
- service nfs start
- service portmap start
- service dhcpd start
- /usr/sbin/exportfs

14
Documentation/blackfin/bfin-spi-notes.txt Normal file
View file

@ -0,0 +1,14 @@
SPI Chip Select behavior:
With the Blackfin on-chip SPI peripheral, there is some logic tied to the CPHA
bit whether the Slave Select Line is controlled by hardware (CPHA=0) or
controlled by software (CPHA=1). However, the Linux SPI bus driver assumes that
the Slave Select is always under software control and being asserted during
the entire SPI transfer. - And not just bits_per_word duration.
In most cases you can utilize SPI MODE_3 instead of MODE_0 to work-around this
behavior. If your SPI slave device in question requires SPI MODE_0 or MODE_2
timing, you can utilize the GPIO controlled SPI Slave Select option instead.
You can even use the same pin whose peripheral role is a SSEL,
but use it as a GPIO instead.

55
Documentation/blackfin/cachefeatures.txt
View file

@ -1,55 +0,0 @@
/*
* File: Documentation/blackfin/cachefeatures.txt
* Based on:
* Author:
*
* Created:
* Description: This file contains the simple DMA Implementation for Blackfin
*
* Rev: $Id: cachefeatures.txt 2384 2006-11-01 04:12:43Z magicyang $
*
* Modified:
* Copyright 2004-2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
*/
- Instruction and Data cache initialization.
icache_init();
dcache_init();
- Instruction and Data cache Invalidation Routines, when flushing the
same is not required.
_icache_invalidate();
_dcache_invalidate();
Also, for invalidating the entire instruction and data cache, the below
routines are provided (another method for invalidation, refer page no 267 and 287 of
ADSP-BF533 Hardware Reference manual)
invalidate_entire_dcache();
invalidate_entire_icache();
-External Flushing of Instruction and data cache routines.
flush_instruction_cache();
flush_data_cache();
- Internal Flushing of Instruction and Data Cache.
icplb_flush();
dcplb_flush();
- Miscellaneous cache functions.
flush_cache_all();
flush_cache_mm();
invalidate_dcache_range();
flush_dcache_range();
flush_dcache_page();
flush_cache_range();
flush_cache_page();
invalidate_dcache_range();
flush_page_to_ram();

20
arch/blackfin/Kconfig
View file

@ -25,6 +25,8 @@ config BLACKFIN
def_bool y
select HAVE_ARCH_KGDB
select HAVE_ARCH_TRACEHOOK
select HAVE_DYNAMIC_FTRACE
select HAVE_FTRACE_MCOUNT_RECORD
select HAVE_FUNCTION_GRAPH_TRACER
select HAVE_FUNCTION_TRACER
select HAVE_FUNCTION_TRACE_MCOUNT_TEST
@ -32,6 +34,7 @@ config BLACKFIN
select HAVE_KERNEL_GZIP if RAMKERNEL
select HAVE_KERNEL_BZIP2 if RAMKERNEL
select HAVE_KERNEL_LZMA if RAMKERNEL
select HAVE_KERNEL_LZO if RAMKERNEL
select HAVE_OPROFILE
select ARCH_WANT_OPTIONAL_GPIOLIB
@ -328,11 +331,6 @@ config BF53x
depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
default y
config MEM_GENERIC_BOARD
bool
depends on GENERIC_BOARD
default y
config MEM_MT48LC64M4A2FB_7E
bool
depends on (BFIN533_STAMP)
@ -850,6 +848,18 @@ config CPLB_SWITCH_TAB_L1
If enabled, the CPLB Switch Tables are linked
into L1 data memory. (less latency)
config CACHE_FLUSH_L1
bool "Locate cache flush funcs in L1 Inst Memory"
default y
help
If enabled, the Blackfin cache flushing functions are linked
into L1 instruction memory.
Note that this might be required to address anomalies, but
these functions are pretty small, so it shouldn't be too bad.
If you are using a processor affected by an anomaly, the build
system will double check for you and prevent it.
config APP_STACK_L1
bool "Support locating application stack in L1 Scratch Memory"
default y

3
arch/blackfin/Makefile
View file

@ -140,7 +140,7 @@ archclean:
INSTALL_PATH ?= /tftpboot
boot := arch/$(ARCH)/boot
BOOT_TARGETS = vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.xip
BOOT_TARGETS = vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.lzo vmImage.xip
PHONY += $(BOOT_TARGETS) install
KBUILD_IMAGE := $(boot)/vmImage
@ -158,6 +158,7 @@ define archhelp
echo ' vmImage.bz2 - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)'
echo '* vmImage.gz - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)'
echo ' vmImage.lzma - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)'
echo ' vmImage.lzo - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzo)'
echo ' vmImage.xip - XIP Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.xip)'
echo ' install - Install kernel using'
echo ' (your) ~/bin/$(INSTALLKERNEL) or'

11
arch/blackfin/boot/Makefile
View file

@ -8,8 +8,8 @@
MKIMAGE := $(srctree)/scripts/mkuboot.sh
targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.xip
extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.xip
targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.lzo vmImage.xip
extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.xip
UIMAGE_OPTS-y :=
UIMAGE_OPTS-$(CONFIG_RAMKERNEL) += -a $(CONFIG_BOOT_LOAD)
@ -33,6 +33,9 @@ $(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
$(call if_changed,lzma)
$(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE
$(call if_changed,lzo)
# The mkimage tool wants 64bytes prepended to the image
quiet_cmd_mk_bin_xip = BIN $@
cmd_mk_bin_xip = ( printf '%64s' | tr ' ' '\377' ; cat $< ) > $@
@ -51,6 +54,9 @@ $(obj)/vmImage.gz: $(obj)/vmlinux.bin.gz
$(obj)/vmImage.lzma: $(obj)/vmlinux.bin.lzma
$(call if_changed,uimage,lzma)
$(obj)/vmImage.lzo: $(obj)/vmlinux.bin.lzo
$(call if_changed,uimage,lzo)
$(obj)/vmImage.xip: $(obj)/vmlinux.bin.xip
$(call if_changed,uimage,none)
@ -58,6 +64,7 @@ suffix-y := bin
suffix-$(CONFIG_KERNEL_GZIP) := gz
suffix-$(CONFIG_KERNEL_BZIP2) := bz2
suffix-$(CONFIG_KERNEL_LZMA) := lzma
suffix-$(CONFIG_KERNEL_LZO) := lzo
suffix-$(CONFIG_ROMKERNEL) := xip
$(obj)/vmImage: $(obj)/vmImage.$(suffix-y)

163
arch/blackfin/configs/BF518F-EZBRD_defconfig
View file

@ -1,7 +1,9 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32.2
# Linux kernel version: 2.6.34.1
# Sun Aug 1 22:52:24 2010
#
CONFIG_SYMBOL_PREFIX="_"
# CONFIG_MMU is not set
# CONFIG_FPU is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
@ -34,9 +36,11 @@ CONFIG_LOCALVERSION_AUTO=y
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_BZIP2=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
@ -49,6 +53,7 @@ CONFIG_SYSVIPC_SYSCTL=y
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_TINY_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
@ -56,8 +61,6 @@ CONFIG_RCU_FANOUT=32
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
@ -66,6 +69,7 @@ CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
@ -98,6 +102,7 @@ CONFIG_SLAB=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
#
# GCOV-based kernel profiling
@ -106,6 +111,7 @@ CONFIG_HAVE_OPROFILE=y
# CONFIG_SLOW_WORK is not set
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
@ -122,14 +128,41 @@ CONFIG_BLOCK=y
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
@ -185,6 +218,7 @@ CONFIG_BF_REV_0_0=y
CONFIG_MEM_MT48LC32M8A2_75=y
CONFIG_BF51x=y
CONFIG_BFIN518F_EZBRD=y
# CONFIG_BFIN518F_TCM is not set
#
# BF518 Specific Configuration
@ -200,6 +234,11 @@ CONFIG_BF518_SPORT0_TSCLK_PG10=y
CONFIG_BF518_UART1_PORTF=y
# CONFIG_BF518_UART1_PORTG is not set
#
# Hysteresis/schmitt Trigger Control
#
# CONFIG_BFIN_HYSTERESIS_CONTROL is not set
#
# Interrupt Priority Assignment
#
@ -288,8 +327,16 @@ CONFIG_HZ=250
# CONFIG_SCHED_HRTICK is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
#
# Clock event device
#
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
#
# Clock souce
#
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
# CONFIG_NO_HZ is not set
@ -320,12 +367,17 @@ CONFIG_ARITHMETIC_OPS_L1=y
CONFIG_ACCESS_OK_L1=y
# CONFIG_MEMSET_L1 is not set
# CONFIG_MEMCPY_L1 is not set
CONFIG_STRCMP_L1=y
CONFIG_STRNCMP_L1=y
CONFIG_STRCPY_L1=y
CONFIG_STRNCPY_L1=y
# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
# CONFIG_IP_CHECKSUM_L1 is not set
CONFIG_CACHELINE_ALIGNED_L1=y
# CONFIG_SYSCALL_TAB_L1 is not set
# CONFIG_CPLB_SWITCH_TAB_L1 is not set
CONFIG_APP_STACK_L1=y
CONFIG_CACHE_FLUSH_L1=y
# CONFIG_EXCEPTION_L1_SCRATCH is not set
#
# Speed Optimizations
@ -425,7 +477,6 @@ CONFIG_NET=y
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
@ -486,6 +537,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_SIR_BFIN_DMA is not set
# CONFIG_SIR_BFIN_PIO is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
# CONFIG_WIRELESS is not set
@ -596,6 +649,10 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
@ -609,6 +666,9 @@ CONFIG_MISC_DEVICES=y
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_ISL29003 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_DS1682 is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_C2PORT is not set
#
@ -619,12 +679,14 @@ CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_IWMC3200TOP is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
@ -656,6 +718,7 @@ CONFIG_PHYLIB=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
@ -663,7 +726,6 @@ CONFIG_MII=y
CONFIG_BFIN_MAC=y
CONFIG_BFIN_TX_DESC_NUM=10
CONFIG_BFIN_RX_DESC_NUM=20
# CONFIG_BFIN_MAC_RMII is not set
CONFIG_BFIN_MAC_USE_HWSTAMP=y
# CONFIG_SMC91X is not set
# CONFIG_DM9000 is not set
@ -702,32 +764,7 @@ CONFIG_BFIN_MAC_USE_HWSTAMP=y
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_UINPUT is not set
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT is not set
#
# Hardware I/O ports
@ -745,11 +782,7 @@ CONFIG_BFIN_DMA_INTERFACE=m
# CONFIG_BFIN_SPI_ADC is not set
# CONFIG_BFIN_SPORT is not set
# CONFIG_BFIN_TWI_LCD is not set
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_VT is not set
# CONFIG_DEVKMEM is not set
CONFIG_BFIN_JTAG_COMM=m
# CONFIG_SERIAL_NONSTANDARD is not set
@ -773,6 +806,7 @@ CONFIG_SERIAL_BFIN_UART0=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_BFIN_SPORT is not set
# CONFIG_SERIAL_TIMBERDALE is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
@ -801,6 +835,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set
#
# External I2C/SMBus adapter drivers
@ -813,16 +848,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
@ -835,6 +863,8 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_BFIN_SPORT is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set
#
# SPI Protocol Masters
@ -854,10 +884,12 @@ CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
# CONFIG_GPIO_IT8761E is not set
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
@ -900,20 +932,25 @@ CONFIG_SSB_POSSIBLE=y
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_TPS65010 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_AB3100_CORE is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_AB4500_CORE is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
@ -929,13 +966,7 @@ CONFIG_SSB_POSSIBLE=y
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
# CONFIG_SOUND is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
@ -953,10 +984,8 @@ CONFIG_MMC_BLOCK_BOUNCE=y
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_AT91 is not set
# CONFIG_MMC_ATMELMCI is not set
# CONFIG_MMC_SPI is not set
CONFIG_SDH_BFIN=m
CONFIG_SDH_BFIN=y
CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
@ -989,6 +1018,7 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
@ -1017,7 +1047,9 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
@ -1050,7 +1082,6 @@ CONFIG_EXT2_FS=m
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
@ -1102,6 +1133,7 @@ CONFIG_MISC_FILESYSTEMS=y
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_LOGFS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
@ -1126,6 +1158,7 @@ CONFIG_SUNRPC=m
# CONFIG_RPCSEC_GSS_SPKM3 is not set
CONFIG_SMB_FS=m
# CONFIG_SMB_NLS_DEFAULT is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
@ -1204,6 +1237,8 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
@ -1227,17 +1262,20 @@ CONFIG_DEBUG_INFO=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TRACEHOOK_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_LKDTM is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_BRANCH_PROFILE_NONE is not set
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
@ -1264,6 +1302,7 @@ CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
# CONFIG_BFIN_ISRAM_SELF_TEST is not set
# CONFIG_BFIN_PSEUDODBG_INSNS is not set
#
# Security options
@ -1273,8 +1312,12 @@ CONFIG_SECURITY=y
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_NETWORK is not set
# CONFIG_SECURITY_PATH is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y
#

129
arch/blackfin/configs/BF526-EZBRD_defconfig
View file

@ -1,7 +1,8 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32.2
# Linux kernel version: 2.6.34
#
CONFIG_SYMBOL_PREFIX="_"
# CONFIG_MMU is not set
# CONFIG_FPU is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_TINY_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
@ -98,6 +100,7 @@ CONFIG_SLAB=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
#
# GCOV-based kernel profiling
@ -106,6 +109,7 @@ CONFIG_HAVE_OPROFILE=y
# CONFIG_SLOW_WORK is not set
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
@ -122,14 +126,41 @@ CONFIG_BLOCK=y
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
@ -232,6 +263,7 @@ CONFIG_BF52x=y
# CONFIG_BFIN527_EZKIT_V2 is not set
# CONFIG_BFIN527_BLUETECHNIX_CM is not set
CONFIG_BFIN526_EZBRD=y
# CONFIG_BFIN527_AD7160EVAL is not set
#
# BF527 Specific Configuration
@ -294,8 +326,16 @@ CONFIG_HZ=250
# CONFIG_SCHED_HRTICK is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
#
# Clock event device
#
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
#
# Clock souce
#
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
# CONFIG_NO_HZ is not set
@ -326,12 +366,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
CONFIG_ACCESS_OK_L1=y
# CONFIG_MEMSET_L1 is not set
# CONFIG_MEMCPY_L1 is not set
CONFIG_STRCMP_L1=y
CONFIG_STRNCMP_L1=y
CONFIG_STRCPY_L1=y
CONFIG_STRNCPY_L1=y
# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
# CONFIG_IP_CHECKSUM_L1 is not set
CONFIG_CACHELINE_ALIGNED_L1=y
# CONFIG_SYSCALL_TAB_L1 is not set
# CONFIG_CPLB_SWITCH_TAB_L1 is not set
CONFIG_APP_STACK_L1=y
CONFIG_CACHE_FLUSH_L1=y
#
# Speed Optimizations
@ -431,7 +475,6 @@ CONFIG_NET=y
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
@ -614,6 +657,10 @@ CONFIG_MTD_NAND_IDS=m
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y
@ -628,6 +675,9 @@ CONFIG_MISC_DEVICES=y
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_ISL29003 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_DS1682 is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_C2PORT is not set
#
@ -644,6 +694,7 @@ CONFIG_HAVE_IDE=y
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
@ -705,6 +756,7 @@ CONFIG_PHYLIB=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
@ -712,7 +764,6 @@ CONFIG_MII=y
CONFIG_BFIN_MAC=y
CONFIG_BFIN_TX_DESC_NUM=10
CONFIG_BFIN_RX_DESC_NUM=20
CONFIG_BFIN_MAC_RMII=y
# CONFIG_SMC91X is not set
# CONFIG_DM9000 is not set
# CONFIG_ENC28J60 is not set
@ -747,6 +798,7 @@ CONFIG_BFIN_MAC_RMII=y
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_IPHETH is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
@ -762,6 +814,7 @@ CONFIG_BFIN_MAC_RMII=y
CONFIG_INPUT=y
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
#
# Userland interfaces
@ -780,6 +833,7 @@ CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATI_REMOTE is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
@ -787,11 +841,10 @@ CONFIG_INPUT_MISC=y
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_BFIN_ROTARY is not set
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_PCF8574 is not set
#
# Hardware I/O ports
@ -837,6 +890,7 @@ CONFIG_SERIAL_BFIN_UART1=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_BFIN_SPORT is not set
# CONFIG_SERIAL_TIMBERDALE is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
@ -865,6 +919,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set
#
# External I2C/SMBus adapter drivers
@ -878,16 +933,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
@ -900,6 +948,8 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_BFIN_SPORT is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set
#
# SPI Protocol Masters
@ -919,10 +969,12 @@ CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
# CONFIG_GPIO_IT8761E is not set
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
@ -960,10 +1012,11 @@ CONFIG_HWMON=y
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7473 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
@ -975,6 +1028,7 @@ CONFIG_HWMON=y
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
@ -1000,6 +1054,7 @@ CONFIG_HWMON=y
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
@ -1013,6 +1068,7 @@ CONFIG_HWMON=y
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_THERMAL is not set
CONFIG_WATCHDOG=y
# CONFIG_WATCHDOG_NOWAYOUT is not set
@ -1038,20 +1094,25 @@ CONFIG_SSB_POSSIBLE=y
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_TPS65010 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_AB3100_CORE is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_AB4500_CORE is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
@ -1087,6 +1148,7 @@ CONFIG_USB_HID=y
#
# Special HID drivers
#
# CONFIG_HID_3M_PCT is not set
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
@ -1102,14 +1164,19 @@ CONFIG_HID_GYRATION=y
CONFIG_HID_LOGITECH=y
# CONFIG_LOGITECH_FF is not set
# CONFIG_LOGIRUMBLEPAD2_FF is not set
# CONFIG_LOGIG940_FF is not set
CONFIG_HID_MICROSOFT=y
# CONFIG_HID_MOSART is not set
CONFIG_HID_MONTEREY=y
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_ORTEK is not set
CONFIG_HID_PANTHERLORD=y
# CONFIG_PANTHERLORD_FF is not set
CONFIG_HID_PETALYNX=y
# CONFIG_HID_QUANTA is not set
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
# CONFIG_HID_STANTUM is not set
CONFIG_HID_SUNPLUS=y
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
@ -1130,7 +1197,6 @@ CONFIG_USB=y
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
CONFIG_USB_OTG_BLACKLIST_HUB=y
CONFIG_USB_MON=y
@ -1214,7 +1280,6 @@ CONFIG_USB_STORAGE=y
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
@ -1227,7 +1292,6 @@ CONFIG_USB_STORAGE=y
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_VST is not set
# CONFIG_USB_GADGET is not set
#
@ -1268,6 +1332,7 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
@ -1296,7 +1361,9 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
@ -1329,7 +1396,6 @@ CONFIG_EXT2_FS=m
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
@ -1393,6 +1459,7 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_LOGFS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
@ -1417,6 +1484,7 @@ CONFIG_SUNRPC=m
# CONFIG_RPCSEC_GSS_SPKM3 is not set
CONFIG_SMB_FS=m
# CONFIG_SMB_NLS_DEFAULT is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
@ -1495,6 +1563,8 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
@ -1518,17 +1588,18 @@ CONFIG_DEBUG_INFO=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TRACEHOOK_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_LKDTM is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_BRANCH_PROFILE_NONE is not set
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
@ -1555,6 +1626,7 @@ CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
# CONFIG_BFIN_ISRAM_SELF_TEST is not set
# CONFIG_BFIN_PSEUDODBG_INSNS is not set
#
# Security options
@ -1564,9 +1636,12 @@ CONFIG_SECURITY=y
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_NETWORK is not set
# CONFIG_SECURITY_PATH is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_SECURITY_ROOTPLUG is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y
#

149
arch/blackfin/configs/BF527-EZKIT-V2_defconfig
View file

@ -1,7 +1,8 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32.2
# Linux kernel version: 2.6.34
#
CONFIG_SYMBOL_PREFIX="_"
# CONFIG_MMU is not set
# CONFIG_FPU is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_TINY_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
@ -98,6 +100,7 @@ CONFIG_SLAB=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
#
# GCOV-based kernel profiling
@ -106,6 +109,7 @@ CONFIG_HAVE_OPROFILE=y
# CONFIG_SLOW_WORK is not set
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
@ -122,14 +126,41 @@ CONFIG_BLOCK=y
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_DEFAULT_IOSCHED="cfq"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
@ -232,6 +263,7 @@ CONFIG_BF52x=y
CONFIG_BFIN527_EZKIT_V2=y
# CONFIG_BFIN527_BLUETECHNIX_CM is not set
# CONFIG_BFIN526_EZBRD is not set
# CONFIG_BFIN527_AD7160EVAL is not set
#
# BF527 Specific Configuration
@ -294,8 +326,16 @@ CONFIG_HZ=250
# CONFIG_SCHED_HRTICK is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
#
# Clock event device
#
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
#
# Clock souce
#
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
# CONFIG_NO_HZ is not set
@ -326,12 +366,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
CONFIG_ACCESS_OK_L1=y
# CONFIG_MEMSET_L1 is not set
# CONFIG_MEMCPY_L1 is not set
CONFIG_STRCMP_L1=y
CONFIG_STRNCMP_L1=y
CONFIG_STRCPY_L1=y
CONFIG_STRNCPY_L1=y
# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
# CONFIG_IP_CHECKSUM_L1 is not set
CONFIG_CACHELINE_ALIGNED_L1=y
# CONFIG_SYSCALL_TAB_L1 is not set
# CONFIG_CPLB_SWITCH_TAB_L1 is not set
CONFIG_APP_STACK_L1=y
CONFIG_CACHE_FLUSH_L1=y
#
# Speed Optimizations
@ -431,7 +475,6 @@ CONFIG_NET=y
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
@ -654,6 +697,10 @@ CONFIG_MTD_NAND_IDS=m
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y
@ -668,6 +715,9 @@ CONFIG_MISC_DEVICES=y
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_ISL29003 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_DS1682 is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_C2PORT is not set
#
@ -684,6 +734,7 @@ CONFIG_HAVE_IDE=y
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
@ -745,6 +796,7 @@ CONFIG_PHYLIB=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
@ -753,7 +805,6 @@ CONFIG_BFIN_MAC=y
CONFIG_BFIN_MAC_USE_L1=y
CONFIG_BFIN_TX_DESC_NUM=10
CONFIG_BFIN_RX_DESC_NUM=20
CONFIG_BFIN_MAC_RMII=y
# CONFIG_SMC91X is not set
# CONFIG_DM9000 is not set
# CONFIG_ENC28J60 is not set
@ -788,6 +839,7 @@ CONFIG_BFIN_MAC_RMII=y
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_IPHETH is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
@ -803,6 +855,7 @@ CONFIG_BFIN_MAC_RMII=y
CONFIG_INPUT=y
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
#
# Userland interfaces
@ -836,8 +889,11 @@ CONFIG_KEYBOARD_ADP5520=y
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_AD7877 is not set
CONFIG_TOUCHSCREEN_AD7879_I2C=y
CONFIG_TOUCHSCREEN_AD7879=y
CONFIG_TOUCHSCREEN_AD7879_I2C=y
# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
# CONFIG_TOUCHSCREEN_AD7160 is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
@ -855,6 +911,7 @@ CONFIG_TOUCHSCREEN_AD7879=y
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATI_REMOTE is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
@ -862,11 +919,10 @@ CONFIG_INPUT_MISC=y
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_BFIN_ROTARY is not set
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_PCF8574 is not set
#
# Hardware I/O ports
@ -912,6 +968,7 @@ CONFIG_SERIAL_BFIN_UART1=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_BFIN_SPORT is not set
# CONFIG_SERIAL_TIMBERDALE is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
@ -940,6 +997,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set
#
# External I2C/SMBus adapter drivers
@ -953,16 +1011,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
@ -975,6 +1026,8 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_BFIN_SPORT is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set
#
# SPI Protocol Masters
@ -994,10 +1047,12 @@ CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
# CONFIG_GPIO_IT8761E is not set
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
@ -1046,21 +1101,26 @@ CONFIG_SSB_POSSIBLE=y
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_UCB1400_CORE is not set
# CONFIG_TPS65010 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_PMIC_DA903X is not set
CONFIG_PMIC_ADP5520=y
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_AB3100_CORE is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_AB4500_CORE is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
@ -1101,6 +1161,7 @@ CONFIG_FB_BFIN_LQ035Q1=y
# CONFIG_FB_BROADSHEET is not set
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_L4F00242T03 is not set
# CONFIG_LCD_LMS283GF05 is not set
# CONFIG_LCD_LTV350QV is not set
# CONFIG_LCD_ILI9320 is not set
@ -1110,6 +1171,7 @@ CONFIG_LCD_CLASS_DEVICE=m
CONFIG_BACKLIGHT_CLASS_DEVICE=m
CONFIG_BACKLIGHT_GENERIC=m
# CONFIG_BACKLIGHT_ADP5520 is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
#
@ -1158,13 +1220,9 @@ CONFIG_SND_DRIVERS=y
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
CONFIG_SND_SPI=y
#
# ALSA Blackfin devices
#
# CONFIG_SND_BFIN_AD73322 is not set
CONFIG_SND_USB=y
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_UA101 is not set
# CONFIG_SND_USB_CAIAQ is not set
CONFIG_SND_SOC=m
CONFIG_SND_SOC_AC97_BUS=y
@ -1173,6 +1231,10 @@ CONFIG_SND_BF5XX_SOC_SSM2602=m
# CONFIG_SND_BF5XX_SOC_AD73311 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1361 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1381 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1373 is not set
# CONFIG_SND_BF5XX_SOC_ADAV80X is not set
# CONFIG_SND_BF5XX_TDM is not set
CONFIG_SND_BF5XX_AC97=m
CONFIG_SND_BF5XX_MMAP_SUPPORT=y
@ -1203,6 +1265,7 @@ CONFIG_USB_HID=y
#
# Special HID drivers
#
# CONFIG_HID_3M_PCT is not set
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
@ -1218,14 +1281,19 @@ CONFIG_HID_GYRATION=y
CONFIG_HID_LOGITECH=y
# CONFIG_LOGITECH_FF is not set
# CONFIG_LOGIRUMBLEPAD2_FF is not set
# CONFIG_LOGIG940_FF is not set
CONFIG_HID_MICROSOFT=y
# CONFIG_HID_MOSART is not set
CONFIG_HID_MONTEREY=y
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_ORTEK is not set
CONFIG_HID_PANTHERLORD=y
# CONFIG_PANTHERLORD_FF is not set
CONFIG_HID_PETALYNX=y
# CONFIG_HID_QUANTA is not set
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
# CONFIG_HID_STANTUM is not set
CONFIG_HID_SUNPLUS=y
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
@ -1246,7 +1314,6 @@ CONFIG_USB=y
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
CONFIG_USB_OTG_BLACKLIST_HUB=y
CONFIG_USB_MON=y
@ -1330,7 +1397,6 @@ CONFIG_USB_STORAGE=y
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
@ -1343,7 +1409,6 @@ CONFIG_USB_STORAGE=y
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_VST is not set
# CONFIG_USB_GADGET is not set
#
@ -1366,11 +1431,8 @@ CONFIG_LEDS_CLASS=y
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_DAC124S085 is not set
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_LT3593 is not set
CONFIG_LEDS_ADP5520=y
#
# LED Triggers
#
# CONFIG_LEDS_TRIGGERS is not set
# CONFIG_ACCESSIBILITY is not set
CONFIG_RTC_LIB=y
@ -1401,6 +1463,7 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
@ -1429,7 +1492,9 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
@ -1462,7 +1527,6 @@ CONFIG_EXT2_FS=m
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
@ -1527,6 +1591,7 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_LOGFS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
@ -1551,6 +1616,7 @@ CONFIG_SUNRPC=m
# CONFIG_RPCSEC_GSS_SPKM3 is not set
CONFIG_SMB_FS=m
# CONFIG_SMB_NLS_DEFAULT is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
@ -1629,6 +1695,8 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
@ -1652,17 +1720,18 @@ CONFIG_DEBUG_INFO=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TRACEHOOK_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_LKDTM is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_BRANCH_PROFILE_NONE is not set
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
@ -1689,6 +1758,7 @@ CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
# CONFIG_BFIN_ISRAM_SELF_TEST is not set
# CONFIG_BFIN_PSEUDODBG_INSNS is not set
#
# Security options
@ -1698,9 +1768,12 @@ CONFIG_SECURITY=y
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_NETWORK is not set
# CONFIG_SECURITY_PATH is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_SECURITY_ROOTPLUG is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y
#

139
arch/blackfin/configs/BF527-EZKIT_defconfig
View file

@ -1,7 +1,8 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32.2
# Linux kernel version: 2.6.34
#
CONFIG_SYMBOL_PREFIX="_"
# CONFIG_MMU is not set
# CONFIG_FPU is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_TINY_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
@ -98,6 +100,7 @@ CONFIG_SLAB=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
#
# GCOV-based kernel profiling
@ -106,6 +109,7 @@ CONFIG_HAVE_OPROFILE=y
# CONFIG_SLOW_WORK is not set
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
@ -122,14 +126,41 @@ CONFIG_BLOCK=y
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_DEFAULT_IOSCHED="cfq"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
@ -232,6 +263,7 @@ CONFIG_BFIN527_EZKIT=y
# CONFIG_BFIN527_EZKIT_V2 is not set
# CONFIG_BFIN527_BLUETECHNIX_CM is not set
# CONFIG_BFIN526_EZBRD is not set
# CONFIG_BFIN527_AD7160EVAL is not set
#
# BF527 Specific Configuration
@ -294,8 +326,16 @@ CONFIG_HZ=250
# CONFIG_SCHED_HRTICK is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
#
# Clock event device
#
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
#
# Clock souce
#
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
# CONFIG_NO_HZ is not set
@ -326,12 +366,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
CONFIG_ACCESS_OK_L1=y
# CONFIG_MEMSET_L1 is not set
# CONFIG_MEMCPY_L1 is not set
CONFIG_STRCMP_L1=y
CONFIG_STRNCMP_L1=y
CONFIG_STRCPY_L1=y
CONFIG_STRNCPY_L1=y
# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
# CONFIG_IP_CHECKSUM_L1 is not set
CONFIG_CACHELINE_ALIGNED_L1=y
# CONFIG_SYSCALL_TAB_L1 is not set
# CONFIG_CPLB_SWITCH_TAB_L1 is not set
CONFIG_APP_STACK_L1=y
CONFIG_CACHE_FLUSH_L1=y
#
# Speed Optimizations
@ -431,7 +475,6 @@ CONFIG_NET=y
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
@ -654,6 +697,10 @@ CONFIG_MTD_NAND_IDS=m
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y
@ -668,6 +715,9 @@ CONFIG_MISC_DEVICES=y
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_ISL29003 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_DS1682 is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_C2PORT is not set
#
@ -684,6 +734,7 @@ CONFIG_HAVE_IDE=y
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
@ -745,6 +796,7 @@ CONFIG_PHYLIB=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
@ -753,7 +805,6 @@ CONFIG_BFIN_MAC=y
CONFIG_BFIN_MAC_USE_L1=y
CONFIG_BFIN_TX_DESC_NUM=10
CONFIG_BFIN_RX_DESC_NUM=20
CONFIG_BFIN_MAC_RMII=y
# CONFIG_SMC91X is not set
# CONFIG_DM9000 is not set
# CONFIG_ENC28J60 is not set
@ -788,6 +839,7 @@ CONFIG_BFIN_MAC_RMII=y
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_IPHETH is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
@ -803,6 +855,7 @@ CONFIG_BFIN_MAC_RMII=y
CONFIG_INPUT=y
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
#
# Userland interfaces
@ -821,6 +874,7 @@ CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATI_REMOTE is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
@ -828,11 +882,10 @@ CONFIG_INPUT_MISC=y
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_BFIN_ROTARY is not set
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_PCF8574 is not set
#
# Hardware I/O ports
@ -878,6 +931,7 @@ CONFIG_SERIAL_BFIN_UART1=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_BFIN_SPORT is not set
# CONFIG_SERIAL_TIMBERDALE is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
@ -906,6 +960,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set
#
# External I2C/SMBus adapter drivers
@ -919,16 +974,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
@ -941,6 +989,8 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_BFIN_SPORT is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set
#
# SPI Protocol Masters
@ -960,10 +1010,12 @@ CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
# CONFIG_GPIO_IT8761E is not set
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
@ -1011,21 +1063,26 @@ CONFIG_SSB_POSSIBLE=y
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_UCB1400_CORE is not set
# CONFIG_TPS65010 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_AB3100_CORE is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_AB4500_CORE is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
@ -1066,6 +1123,7 @@ CONFIG_FB_BFIN_T350MCQB=y
# CONFIG_FB_BROADSHEET is not set
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_L4F00242T03 is not set
# CONFIG_LCD_LMS283GF05 is not set
CONFIG_LCD_LTV350QV=m
# CONFIG_LCD_ILI9320 is not set
@ -1074,6 +1132,7 @@ CONFIG_LCD_LTV350QV=m
# CONFIG_LCD_PLATFORM is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=m
CONFIG_BACKLIGHT_GENERIC=m
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
#
@ -1122,13 +1181,9 @@ CONFIG_SND_DRIVERS=y
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
CONFIG_SND_SPI=y
#
# ALSA Blackfin devices
#
# CONFIG_SND_BFIN_AD73322 is not set
CONFIG_SND_USB=y
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_UA101 is not set
# CONFIG_SND_USB_CAIAQ is not set
CONFIG_SND_SOC=m
CONFIG_SND_SOC_AC97_BUS=y
@ -1137,6 +1192,10 @@ CONFIG_SND_BF5XX_SOC_SSM2602=m
# CONFIG_SND_BF5XX_SOC_AD73311 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1361 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1381 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1373 is not set
# CONFIG_SND_BF5XX_SOC_ADAV80X is not set
# CONFIG_SND_BF5XX_TDM is not set
CONFIG_SND_BF5XX_AC97=m
CONFIG_SND_BF5XX_MMAP_SUPPORT=y
@ -1167,6 +1226,7 @@ CONFIG_USB_HID=y
#
# Special HID drivers
#
# CONFIG_HID_3M_PCT is not set
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
@ -1182,14 +1242,19 @@ CONFIG_HID_GYRATION=y
CONFIG_HID_LOGITECH=y
# CONFIG_LOGITECH_FF is not set
# CONFIG_LOGIRUMBLEPAD2_FF is not set
# CONFIG_LOGIG940_FF is not set
CONFIG_HID_MICROSOFT=y
# CONFIG_HID_MOSART is not set
CONFIG_HID_MONTEREY=y
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_ORTEK is not set
CONFIG_HID_PANTHERLORD=y
# CONFIG_PANTHERLORD_FF is not set
CONFIG_HID_PETALYNX=y
# CONFIG_HID_QUANTA is not set
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
# CONFIG_HID_STANTUM is not set
CONFIG_HID_SUNPLUS=y
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
@ -1210,7 +1275,6 @@ CONFIG_USB=y
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
CONFIG_USB_OTG_BLACKLIST_HUB=y
CONFIG_USB_MON=y
@ -1292,7 +1356,6 @@ CONFIG_USB_STORAGE=y
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
@ -1305,7 +1368,6 @@ CONFIG_USB_STORAGE=y
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_VST is not set
# CONFIG_USB_GADGET is not set
#
@ -1346,6 +1408,7 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
@ -1374,7 +1437,9 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
@ -1407,7 +1472,6 @@ CONFIG_EXT2_FS=m
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
@ -1472,6 +1536,7 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_LOGFS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
@ -1496,6 +1561,7 @@ CONFIG_SUNRPC=m
# CONFIG_RPCSEC_GSS_SPKM3 is not set
CONFIG_SMB_FS=m
# CONFIG_SMB_NLS_DEFAULT is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
@ -1574,6 +1640,8 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
@ -1597,17 +1665,18 @@ CONFIG_DEBUG_INFO=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TRACEHOOK_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_LKDTM is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_BRANCH_PROFILE_NONE is not set
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
@ -1634,6 +1703,7 @@ CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
# CONFIG_BFIN_ISRAM_SELF_TEST is not set
# CONFIG_BFIN_PSEUDODBG_INSNS is not set
#
# Security options
@ -1643,9 +1713,12 @@ CONFIG_SECURITY=y
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_NETWORK is not set
# CONFIG_SECURITY_PATH is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_SECURITY_ROOTPLUG is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y
#

93
arch/blackfin/configs/BF533-EZKIT_defconfig
View file

@ -1,7 +1,8 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32.2
# Linux kernel version: 2.6.34
#
CONFIG_SYMBOL_PREFIX="_"
# CONFIG_MMU is not set
# CONFIG_FPU is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_TINY_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
@ -98,6 +100,7 @@ CONFIG_SLAB=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
#
# GCOV-based kernel profiling
@ -122,14 +125,41 @@ CONFIG_BLOCK=y
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_DEFAULT_IOSCHED="cfq"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
@ -254,8 +284,16 @@ CONFIG_HZ=250
CONFIG_SCHED_HRTICK=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
#
# Clock event device
#
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
#
# Clock souce
#
CONFIG_CYCLES_CLOCKSOURCE=y
# CONFIG_GPTMR0_CLOCKSOURCE is not set
CONFIG_TICK_ONESHOT=y
@ -287,12 +325,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
CONFIG_ACCESS_OK_L1=y
CONFIG_MEMSET_L1=y
CONFIG_MEMCPY_L1=y
CONFIG_STRCMP_L1=y
CONFIG_STRNCMP_L1=y
CONFIG_STRCPY_L1=y
CONFIG_STRNCPY_L1=y
CONFIG_SYS_BFIN_SPINLOCK_L1=y
# CONFIG_IP_CHECKSUM_L1 is not set
CONFIG_CACHELINE_ALIGNED_L1=y
# CONFIG_SYSCALL_TAB_L1 is not set
# CONFIG_CPLB_SWITCH_TAB_L1 is not set
CONFIG_APP_STACK_L1=y
CONFIG_CACHE_FLUSH_L1=y
#
# Speed Optimizations
@ -385,10 +427,10 @@ CONFIG_PM_SLEEP=y
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_PM_RUNTIME is not set
CONFIG_PM_OPS=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_PM_BFIN_SLEEP_DEEPER=y
# CONFIG_PM_BFIN_SLEEP is not set
# CONFIG_PM_WAKEUP_BY_GPIO is not set
#
# Possible Suspend Mem / Hibernate Wake-Up Sources
@ -404,7 +446,6 @@ CONFIG_NET=y
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
@ -608,6 +649,10 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
@ -617,7 +662,9 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_BLK_DEV_HD is not set
CONFIG_MISC_DEVICES=y
# CONFIG_AD525X_DPOT is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_C2PORT is not set
#
@ -631,6 +678,7 @@ CONFIG_HAVE_IDE=y
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
@ -687,6 +735,7 @@ CONFIG_SMC91X=y
CONFIG_INPUT=m
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
#
# Userland interfaces
@ -744,6 +793,7 @@ CONFIG_SERIAL_BFIN_UART0=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_BFIN_SPORT is not set
# CONFIG_SERIAL_TIMBERDALE is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
@ -765,6 +815,8 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_BFIN_SPORT is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set
#
# SPI Protocol Masters
@ -784,6 +836,7 @@ CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
# CONFIG_GPIO_IT8761E is not set
#
# I2C GPIO expanders:
@ -831,6 +884,7 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_AB4500_CORE is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
@ -898,7 +952,9 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
@ -929,7 +985,6 @@ CONFIG_RTC_DRV_BFIN=y
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
@ -988,6 +1043,7 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_LOGFS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
@ -1012,6 +1068,7 @@ CONFIG_SUNRPC=m
# CONFIG_RPCSEC_GSS_SPKM3 is not set
CONFIG_SMB_FS=m
# CONFIG_SMB_NLS_DEFAULT is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
@ -1113,17 +1170,18 @@ CONFIG_DEBUG_INFO=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TRACEHOOK_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_LKDTM is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_BRANCH_PROFILE_NONE is not set
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
@ -1150,6 +1208,7 @@ CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
# CONFIG_BFIN_ISRAM_SELF_TEST is not set
# CONFIG_BFIN_PSEUDODBG_INSNS is not set
#
# Security options
@ -1159,8 +1218,12 @@ CONFIG_SECURITY=y
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_NETWORK is not set
# CONFIG_SECURITY_PATH is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y
#

133
arch/blackfin/configs/BF533-STAMP_defconfig
View file

@ -1,7 +1,8 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32.2
# Linux kernel version: 2.6.34
#
CONFIG_SYMBOL_PREFIX="_"
# CONFIG_MMU is not set
# CONFIG_FPU is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_TINY_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
@ -98,6 +100,7 @@ CONFIG_SLAB=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
#
# GCOV-based kernel profiling
@ -106,6 +109,7 @@ CONFIG_HAVE_OPROFILE=y
# CONFIG_SLOW_WORK is not set
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
@ -122,14 +126,41 @@ CONFIG_BLOCK=y
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_DEFAULT_IOSCHED="cfq"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
@ -254,8 +285,16 @@ CONFIG_HZ=250
CONFIG_SCHED_HRTICK=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
#
# Clock event device
#
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
#
# Clock souce
#
CONFIG_CYCLES_CLOCKSOURCE=y
# CONFIG_GPTMR0_CLOCKSOURCE is not set
CONFIG_TICK_ONESHOT=y
@ -287,12 +326,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
CONFIG_ACCESS_OK_L1=y
CONFIG_MEMSET_L1=y
CONFIG_MEMCPY_L1=y
CONFIG_STRCMP_L1=y
CONFIG_STRNCMP_L1=y
CONFIG_STRCPY_L1=y
CONFIG_STRNCPY_L1=y
CONFIG_SYS_BFIN_SPINLOCK_L1=y
# CONFIG_IP_CHECKSUM_L1 is not set
CONFIG_CACHELINE_ALIGNED_L1=y
# CONFIG_SYSCALL_TAB_L1 is not set
# CONFIG_CPLB_SWITCH_TAB_L1 is not set
CONFIG_APP_STACK_L1=y
CONFIG_CACHE_FLUSH_L1=y
#
# Speed Optimizations
@ -385,10 +428,10 @@ CONFIG_PM_SLEEP=y
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_PM_RUNTIME is not set
CONFIG_PM_OPS=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_PM_BFIN_SLEEP_DEEPER=y
# CONFIG_PM_BFIN_SLEEP is not set
# CONFIG_PM_WAKEUP_BY_GPIO is not set
#
# Possible Suspend Mem / Hibernate Wake-Up Sources
@ -404,7 +447,6 @@ CONFIG_NET=y
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
@ -612,6 +654,10 @@ CONFIG_MTD_BFIN_ASYNC=m
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
@ -625,6 +671,9 @@ CONFIG_MISC_DEVICES=y
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_ISL29003 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_DS1682 is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_C2PORT is not set
#
@ -641,6 +690,7 @@ CONFIG_HAVE_IDE=y
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
@ -697,6 +747,7 @@ CONFIG_SMC91X=y
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
#
# Userland interfaces
@ -715,11 +766,11 @@ CONFIG_INPUT_EVDEV=m
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_UINPUT is not set
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_ADXL34X is not set
#
# Hardware I/O ports
@ -760,6 +811,7 @@ CONFIG_SERIAL_BFIN_UART0=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_BFIN_SPORT is not set
# CONFIG_SERIAL_TIMBERDALE is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
@ -781,9 +833,10 @@ CONFIG_I2C_HELPER_AUTO=y
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_GPIO is not set
CONFIG_I2C_GPIO=m
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set
#
# External I2C/SMBus adapter drivers
@ -796,16 +849,9 @@ CONFIG_I2C_HELPER_AUTO=y
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
@ -818,6 +864,8 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_BFIN_SPORT is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set
#
# SPI Protocol Masters
@ -837,10 +885,12 @@ CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
# CONFIG_GPIO_IT8761E is not set
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
@ -889,12 +939,11 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_TPS65010 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_AB3100_CORE is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_AB4500_CORE is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
@ -977,22 +1026,18 @@ CONFIG_SND_DRIVERS=y
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
CONFIG_SND_SPI=y
#
# ALSA Blackfin devices
#
CONFIG_SND_BFIN_SPORT=0
CONFIG_SND_BFIN_AD73322=m
CONFIG_SND_BFIN_AD73322_SPORT0_SE=10
CONFIG_SND_BFIN_AD73322_SPORT1_SE=14
CONFIG_SND_BFIN_AD73322_RESET=12
CONFIG_SND_SOC=m
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_BF5XX_I2S=m
# CONFIG_SND_BF5XX_SOC_SSM2602 is not set
CONFIG_SND_BF5XX_SOC_AD73311=m
CONFIG_SND_AD7XXXX_SELECT=0
# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1361 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1381 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1373 is not set
# CONFIG_SND_BF5XX_SOC_ADAV80X is not set
CONFIG_SND_BFIN_AD73311_SE=4
# CONFIG_SND_BF5XX_TDM is not set
CONFIG_SND_BF5XX_AC97=m
@ -1051,6 +1096,7 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
@ -1079,7 +1125,9 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
@ -1111,7 +1159,6 @@ CONFIG_RTC_DRV_BFIN=y
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
@ -1170,6 +1217,7 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_LOGFS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
@ -1194,6 +1242,7 @@ CONFIG_SUNRPC=m
# CONFIG_RPCSEC_GSS_SPKM3 is not set
CONFIG_SMB_FS=m
# CONFIG_SMB_NLS_DEFAULT is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
@ -1272,6 +1321,8 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
@ -1295,17 +1346,18 @@ CONFIG_DEBUG_INFO=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TRACEHOOK_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_LKDTM is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_BRANCH_PROFILE_NONE is not set
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
@ -1332,6 +1384,7 @@ CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
# CONFIG_BFIN_ISRAM_SELF_TEST is not set
# CONFIG_BFIN_PSEUDODBG_INSNS is not set
#
# Security options
@ -1341,8 +1394,12 @@ CONFIG_SECURITY=y
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_NETWORK is not set
# CONFIG_SECURITY_PATH is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y
#

143
arch/blackfin/configs/BF537-STAMP_defconfig
View file

@ -1,7 +1,8 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32.2
# Linux kernel version: 2.6.34
#
CONFIG_SYMBOL_PREFIX="_"
# CONFIG_MMU is not set
# CONFIG_FPU is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_TINY_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
@ -98,6 +100,7 @@ CONFIG_SLAB=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
#
# GCOV-based kernel profiling
@ -106,6 +109,7 @@ CONFIG_HAVE_OPROFILE=y
# CONFIG_SLOW_WORK is not set
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
@ -122,14 +126,41 @@ CONFIG_BLOCK=y
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_DEFAULT_IOSCHED="cfq"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
@ -230,7 +261,7 @@ CONFIG_BFIN537_STAMP=y
# Priority
#
CONFIG_IRQ_DMA_ERROR=7
CONFIG_IRQ_ERROR=7
CONFIG_IRQ_ERROR=11
CONFIG_IRQ_CAN_RX=11
CONFIG_IRQ_CAN_TX=11
CONFIG_IRQ_PROG_INTA=12
@ -262,8 +293,16 @@ CONFIG_HZ=250
CONFIG_SCHED_HRTICK=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
#
# Clock event device
#
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
#
# Clock souce
#
CONFIG_CYCLES_CLOCKSOURCE=y
# CONFIG_GPTMR0_CLOCKSOURCE is not set
CONFIG_TICK_ONESHOT=y
@ -295,12 +334,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
CONFIG_ACCESS_OK_L1=y
CONFIG_MEMSET_L1=y
CONFIG_MEMCPY_L1=y
CONFIG_STRCMP_L1=y
CONFIG_STRNCMP_L1=y
CONFIG_STRCPY_L1=y
CONFIG_STRNCPY_L1=y
CONFIG_SYS_BFIN_SPINLOCK_L1=y
# CONFIG_IP_CHECKSUM_L1 is not set
CONFIG_CACHELINE_ALIGNED_L1=y
# CONFIG_SYSCALL_TAB_L1 is not set
# CONFIG_CPLB_SWITCH_TAB_L1 is not set
CONFIG_APP_STACK_L1=y
CONFIG_CACHE_FLUSH_L1=y
#
# Speed Optimizations
@ -393,10 +436,10 @@ CONFIG_PM_SLEEP=y
CONFIG_SUSPEND=y
CONFIG_SUSPEND_FREEZER=y
# CONFIG_PM_RUNTIME is not set
CONFIG_PM_OPS=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_PM_BFIN_SLEEP_DEEPER=y
# CONFIG_PM_BFIN_SLEEP is not set
# CONFIG_PM_WAKEUP_BY_GPIO is not set
#
# Possible Suspend Mem / Hibernate Wake-Up Sources
@ -413,7 +456,6 @@ CONFIG_NET=y
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
@ -482,13 +524,9 @@ CONFIG_CAN_BCM=m
# CONFIG_CAN_VCAN is not set
CONFIG_CAN_DEV=m
# CONFIG_CAN_CALC_BITTIMING is not set
# CONFIG_CAN_MCP251X is not set
CONFIG_CAN_BFIN=m
# CONFIG_CAN_SJA1000 is not set
#
# CAN USB interfaces
#
# CONFIG_CAN_EMS_USB is not set
# CONFIG_CAN_DEBUG_DEVICES is not set
CONFIG_IRDA=m
@ -638,6 +676,10 @@ CONFIG_MTD_PHYSMAP=m
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
@ -651,6 +693,9 @@ CONFIG_MISC_DEVICES=y
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_ISL29003 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_DS1682 is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_C2PORT is not set
#
@ -667,6 +712,7 @@ CONFIG_HAVE_IDE=y
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
@ -698,6 +744,7 @@ CONFIG_SMSC_PHY=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
@ -706,7 +753,6 @@ CONFIG_BFIN_MAC=y
CONFIG_BFIN_MAC_USE_L1=y
CONFIG_BFIN_TX_DESC_NUM=10
CONFIG_BFIN_RX_DESC_NUM=20
# CONFIG_BFIN_MAC_RMII is not set
# CONFIG_SMC91X is not set
# CONFIG_DM9000 is not set
# CONFIG_ENC28J60 is not set
@ -747,6 +793,7 @@ CONFIG_BFIN_RX_DESC_NUM=20
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
#
# Userland interfaces
@ -765,11 +812,11 @@ CONFIG_INPUT_EVDEV=m
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_UINPUT is not set
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_ADXL34X is not set
#
# Hardware I/O ports
@ -811,6 +858,7 @@ CONFIG_SERIAL_BFIN_UART0=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_BFIN_SPORT is not set
# CONFIG_SERIAL_TIMBERDALE is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
@ -837,6 +885,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set
#
# External I2C/SMBus adapter drivers
@ -849,16 +898,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
@ -871,6 +913,8 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_BFIN_SPORT is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set
#
# SPI Protocol Masters
@ -890,10 +934,12 @@ CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
# CONFIG_GPIO_IT8761E is not set
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
@ -942,12 +988,11 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_TPS65010 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_AB3100_CORE is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_AB4500_CORE is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
@ -998,6 +1043,7 @@ CONFIG_ADV7393_1XMEM=y
# CONFIG_FB_BROADSHEET is not set
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_L4F00242T03 is not set
# CONFIG_LCD_LMS283GF05 is not set
# CONFIG_LCD_LTV350QV is not set
# CONFIG_LCD_ILI9320 is not set
@ -1006,6 +1052,7 @@ CONFIG_LCD_CLASS_DEVICE=m
# CONFIG_LCD_PLATFORM is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=m
CONFIG_BACKLIGHT_GENERIC=m
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
#
@ -1042,22 +1089,18 @@ CONFIG_SND_DRIVERS=y
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
CONFIG_SND_SPI=y
#
# ALSA Blackfin devices
#
CONFIG_SND_BFIN_SPORT=0
CONFIG_SND_BFIN_AD73322=m
CONFIG_SND_BFIN_AD73322_SPORT0_SE=10
CONFIG_SND_BFIN_AD73322_SPORT1_SE=14
CONFIG_SND_BFIN_AD73322_RESET=12
CONFIG_SND_SOC=m
CONFIG_SND_SOC_AC97_BUS=y
CONFIG_SND_BF5XX_I2S=m
# CONFIG_SND_BF5XX_SOC_SSM2602 is not set
CONFIG_SND_BF5XX_SOC_AD73311=m
CONFIG_SND_AD7XXXX_SELECT=0
# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1361 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1381 is not set
# CONFIG_SND_BF5XX_SOC_ADAU1373 is not set
# CONFIG_SND_BF5XX_SOC_ADAV80X is not set
CONFIG_SND_BFIN_AD73311_SE=4
# CONFIG_SND_BF5XX_TDM is not set
CONFIG_SND_BF5XX_AC97=m
@ -1116,6 +1159,7 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
@ -1144,7 +1188,9 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
@ -1176,7 +1222,6 @@ CONFIG_RTC_DRV_BFIN=y
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
@ -1235,6 +1280,7 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_LOGFS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
@ -1259,6 +1305,7 @@ CONFIG_SUNRPC=m
# CONFIG_RPCSEC_GSS_SPKM3 is not set
CONFIG_SMB_FS=m
# CONFIG_SMB_NLS_DEFAULT is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
@ -1337,6 +1384,8 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
@ -1360,17 +1409,18 @@ CONFIG_DEBUG_INFO=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TRACEHOOK_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_LKDTM is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_BRANCH_PROFILE_NONE is not set
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
@ -1397,6 +1447,7 @@ CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
# CONFIG_BFIN_ISRAM_SELF_TEST is not set
# CONFIG_BFIN_PSEUDODBG_INSNS is not set
#
# Security options
@ -1406,8 +1457,12 @@ CONFIG_SECURITY=y
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_NETWORK is not set
# CONFIG_SECURITY_PATH is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y
#

123
arch/blackfin/configs/BF538-EZKIT_defconfig
View file

@ -1,7 +1,8 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32.2
# Linux kernel version: 2.6.34
#
CONFIG_SYMBOL_PREFIX="_"
# CONFIG_MMU is not set
# CONFIG_FPU is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_TINY_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
@ -98,6 +100,7 @@ CONFIG_SLAB=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
#
# GCOV-based kernel profiling
@ -106,6 +109,7 @@ CONFIG_HAVE_OPROFILE=y
# CONFIG_SLOW_WORK is not set
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
@ -122,14 +126,41 @@ CONFIG_BLOCK=y
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_DEFAULT_IOSCHED="cfq"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
@ -272,8 +303,16 @@ CONFIG_HZ=250
CONFIG_SCHED_HRTICK=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
#
# Clock event device
#
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
#
# Clock souce
#
CONFIG_CYCLES_CLOCKSOURCE=y
# CONFIG_GPTMR0_CLOCKSOURCE is not set
CONFIG_TICK_ONESHOT=y
@ -305,12 +344,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
CONFIG_ACCESS_OK_L1=y
CONFIG_MEMSET_L1=y
CONFIG_MEMCPY_L1=y
CONFIG_STRCMP_L1=y
CONFIG_STRNCMP_L1=y
CONFIG_STRCPY_L1=y
CONFIG_STRNCPY_L1=y
CONFIG_SYS_BFIN_SPINLOCK_L1=y
# CONFIG_IP_CHECKSUM_L1 is not set
CONFIG_CACHELINE_ALIGNED_L1=y
# CONFIG_SYSCALL_TAB_L1 is not set
# CONFIG_CPLB_SWITCH_TAB_L1 is not set
CONFIG_APP_STACK_L1=y
CONFIG_CACHE_FLUSH_L1=y
#
# Speed Optimizations
@ -410,7 +453,6 @@ CONFIG_NET=y
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
@ -479,13 +521,9 @@ CONFIG_CAN_BCM=m
# CONFIG_CAN_VCAN is not set
CONFIG_CAN_DEV=m
# CONFIG_CAN_CALC_BITTIMING is not set
# CONFIG_CAN_MCP251X is not set
CONFIG_CAN_BFIN=m
# CONFIG_CAN_SJA1000 is not set
#
# CAN USB interfaces
#
# CONFIG_CAN_EMS_USB is not set
# CONFIG_CAN_DEBUG_DEVICES is not set
CONFIG_IRDA=m
@ -641,6 +679,10 @@ CONFIG_MTD_NAND_IDS=m
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
@ -656,6 +698,7 @@ CONFIG_HAVE_IDE=y
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
@ -687,6 +730,7 @@ CONFIG_SMSC_PHY=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
@ -731,6 +775,7 @@ CONFIG_SMC91X=y
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
#
# Userland interfaces
@ -750,9 +795,11 @@ CONFIG_INPUT_EVDEV=m
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_AD7877 is not set
CONFIG_TOUCHSCREEN_AD7879=y
# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
CONFIG_TOUCHSCREEN_AD7879_SPI=y
CONFIG_TOUCHSCREEN_AD7879=y
# CONFIG_TOUCHSCREEN_AD7160 is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
@ -768,11 +815,11 @@ CONFIG_TOUCHSCREEN_AD7879=y
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_UINPUT is not set
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_ADXL34X is not set
#
# Hardware I/O ports
@ -817,6 +864,7 @@ CONFIG_SERIAL_BFIN_UART2=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_BFIN_SPORT is not set
# CONFIG_SERIAL_TIMBERDALE is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
@ -843,6 +891,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set
#
# External I2C/SMBus adapter drivers
@ -855,16 +904,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
@ -877,6 +919,8 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_BFIN_SPORT is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set
#
# SPI Protocol Masters
@ -896,10 +940,12 @@ CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
# CONFIG_GPIO_IT8761E is not set
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
@ -947,12 +993,11 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_TPS65010 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_AB3100_CORE is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_AB4500_CORE is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
@ -1040,6 +1085,7 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
@ -1068,7 +1114,9 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
@ -1100,7 +1148,6 @@ CONFIG_RTC_DRV_BFIN=y
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
@ -1159,6 +1206,7 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_LOGFS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
@ -1183,6 +1231,7 @@ CONFIG_SUNRPC=m
# CONFIG_RPCSEC_GSS_SPKM3 is not set
CONFIG_SMB_FS=m
# CONFIG_SMB_NLS_DEFAULT is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
@ -1261,6 +1310,8 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
@ -1284,17 +1335,18 @@ CONFIG_DEBUG_INFO=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TRACEHOOK_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_LKDTM is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_BRANCH_PROFILE_NONE is not set
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
@ -1321,6 +1373,7 @@ CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
# CONFIG_BFIN_ISRAM_SELF_TEST is not set
# CONFIG_BFIN_PSEUDODBG_INSNS is not set
#
# Security options
@ -1330,8 +1383,12 @@ CONFIG_SECURITY=y
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_NETWORK is not set
# CONFIG_SECURITY_PATH is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y
#

156
arch/blackfin/configs/BF548-EZKIT_defconfig
View file

@ -1,7 +1,8 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32.2
# Linux kernel version: 2.6.34
#
CONFIG_SYMBOL_PREFIX="_"
# CONFIG_MMU is not set
# CONFIG_FPU is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_TINY_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
@ -98,6 +100,7 @@ CONFIG_SLAB=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
#
# GCOV-based kernel profiling
@ -107,6 +110,7 @@ CONFIG_SLOW_WORK=y
# CONFIG_SLOW_WORK_DEBUG is not set
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
@ -123,14 +127,41 @@ CONFIG_BLOCK=y
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
@ -330,8 +361,16 @@ CONFIG_HZ=250
# CONFIG_SCHED_HRTICK is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
#
# Clock event device
#
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
#
# Clock souce
#
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
# CONFIG_NO_HZ is not set
@ -362,12 +401,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
CONFIG_ACCESS_OK_L1=y
# CONFIG_MEMSET_L1 is not set
# CONFIG_MEMCPY_L1 is not set
CONFIG_STRCMP_L1=y
CONFIG_STRNCMP_L1=y
CONFIG_STRCPY_L1=y
CONFIG_STRNCPY_L1=y
# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
# CONFIG_IP_CHECKSUM_L1 is not set
CONFIG_CACHELINE_ALIGNED_L1=y
# CONFIG_SYSCALL_TAB_L1 is not set
# CONFIG_CPLB_SWITCH_TAB_L1 is not set
CONFIG_APP_STACK_L1=y
CONFIG_CACHE_FLUSH_L1=y
#
# Speed Optimizations
@ -472,7 +515,6 @@ CONFIG_NET=y
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
@ -540,6 +582,7 @@ CONFIG_CAN_BCM=m
# CONFIG_CAN_VCAN is not set
CONFIG_CAN_DEV=m
# CONFIG_CAN_CALC_BITTIMING is not set
# CONFIG_CAN_MCP251X is not set
CONFIG_CAN_BFIN=m
# CONFIG_CAN_SJA1000 is not set
@ -595,9 +638,14 @@ CONFIG_SIR_BFIN_DMA=y
# CONFIG_MCS_FIR is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
# CONFIG_WIRELESS is not set
CONFIG_WIRELESS_EXT=y
CONFIG_WIRELESS=y
# CONFIG_CFG80211 is not set
CONFIG_LIB80211=m
# CONFIG_LIB80211_DEBUG is not set
#
# CFG80211 needs to be enabled for MAC80211
#
# CONFIG_WIMAX is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
@ -700,8 +748,7 @@ CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
CONFIG_MTD_NAND_IDS=y
CONFIG_MTD_NAND_BF5XX=y
CONFIG_MTD_NAND_BF5XX_HWECC=y
# CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC is not set
# CONFIG_MTD_NAND_BF5XX_HWECC is not set
# CONFIG_MTD_NAND_DISKONCHIP is not set
# CONFIG_MTD_NAND_NANDSIM is not set
# CONFIG_MTD_NAND_PLATFORM is not set
@ -721,6 +768,10 @@ CONFIG_MTD_NAND_BF5XX_HWECC=y
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y
@ -735,6 +786,9 @@ CONFIG_MISC_DEVICES=y
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_ISL29003 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_DS1682 is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_C2PORT is not set
#
@ -745,12 +799,14 @@ CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_IWMC3200TOP is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
@ -819,6 +875,7 @@ CONFIG_PHYLIB=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
@ -844,14 +901,6 @@ CONFIG_SMSC911X=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_WLAN=y
# CONFIG_WLAN_PRE80211 is not set
CONFIG_WLAN_80211=y
CONFIG_LIBERTAS=m
# CONFIG_LIBERTAS_USB is not set
CONFIG_LIBERTAS_SDIO=m
CONFIG_POWEROF2_BLOCKSIZE_ONLY=y
# CONFIG_LIBERTAS_SPI is not set
# CONFIG_LIBERTAS_DEBUG is not set
# CONFIG_USB_ZD1201 is not set
# CONFIG_HOSTAP is not set
@ -867,6 +916,7 @@ CONFIG_POWEROF2_BLOCKSIZE_ONLY=y
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_IPHETH is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
@ -882,6 +932,7 @@ CONFIG_POWEROF2_BLOCKSIZE_ONLY=y
CONFIG_INPUT=y
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
#
# Userland interfaces
@ -914,9 +965,9 @@ CONFIG_KEYBOARD_BFIN=y
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
CONFIG_TOUCHSCREEN_AD7877=m
# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_AD7160 is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
@ -934,6 +985,7 @@ CONFIG_TOUCHSCREEN_AD7877=m
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATI_REMOTE is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
@ -941,11 +993,10 @@ CONFIG_INPUT_MISC=y
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
# CONFIG_INPUT_BFIN_ROTARY is not set
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_PCF8574 is not set
#
# Hardware I/O ports
@ -993,6 +1044,7 @@ CONFIG_SERIAL_BFIN_UART1=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_BFIN_SPORT is not set
# CONFIG_SERIAL_TIMBERDALE is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
@ -1021,6 +1073,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set
#
# External I2C/SMBus adapter drivers
@ -1034,16 +1087,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
@ -1056,6 +1102,8 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_BFIN_SPORT is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set
#
# SPI Protocol Masters
@ -1075,10 +1123,12 @@ CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
# CONFIG_GPIO_IT8761E is not set
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
@ -1126,21 +1176,26 @@ CONFIG_SSB_POSSIBLE=y
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_UCB1400_CORE is not set
# CONFIG_TPS65010 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_AB3100_CORE is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_AB4500_CORE is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
@ -1239,13 +1294,9 @@ CONFIG_SND_DRIVERS=y
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
CONFIG_SND_SPI=y
#
# ALSA Blackfin devices
#
# CONFIG_SND_BFIN_AD73322 is not set
CONFIG_SND_USB=y
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_UA101 is not set
# CONFIG_SND_USB_CAIAQ is not set
CONFIG_SND_SOC=y
CONFIG_SND_SOC_AC97_BUS=y
@ -1279,6 +1330,7 @@ CONFIG_USB_HID=y
#
# Special HID drivers
#
# CONFIG_HID_3M_PCT is not set
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
@ -1294,14 +1346,19 @@ CONFIG_HID_GYRATION=y
CONFIG_HID_LOGITECH=y
# CONFIG_LOGITECH_FF is not set
# CONFIG_LOGIRUMBLEPAD2_FF is not set
# CONFIG_LOGIG940_FF is not set
CONFIG_HID_MICROSOFT=y
# CONFIG_HID_MOSART is not set
CONFIG_HID_MONTEREY=y
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_ORTEK is not set
CONFIG_HID_PANTHERLORD=y
# CONFIG_PANTHERLORD_FF is not set
CONFIG_HID_PETALYNX=y
# CONFIG_HID_QUANTA is not set
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SONY=y
# CONFIG_HID_STANTUM is not set
CONFIG_HID_SUNPLUS=y
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
@ -1322,7 +1379,6 @@ CONFIG_USB=y
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_WHITELIST is not set
CONFIG_USB_OTG_BLACKLIST_HUB=y
CONFIG_USB_MON=y
@ -1406,7 +1462,6 @@ CONFIG_USB_STORAGE=y
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
@ -1419,7 +1474,6 @@ CONFIG_USB_STORAGE=y
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_VST is not set
# CONFIG_USB_GADGET is not set
#
@ -1444,11 +1498,9 @@ CONFIG_MMC_BLOCK_BOUNCE=y
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_AT91 is not set
# CONFIG_MMC_ATMELMCI is not set
# CONFIG_MMC_SPI is not set
CONFIG_SDH_BFIN=y
# CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND is not set
CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND=y
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
@ -1480,6 +1532,7 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
@ -1508,7 +1561,9 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
@ -1609,6 +1664,7 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_LOGFS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
@ -1638,6 +1694,7 @@ CONFIG_SUNRPC=m
CONFIG_SMB_FS=m
CONFIG_SMB_NLS_DEFAULT=y
CONFIG_SMB_NLS_REMOTE="cp437"
# CONFIG_CEPH_FS is not set
CONFIG_CIFS=y
# CONFIG_CIFS_STATS is not set
# CONFIG_CIFS_WEAK_PW_HASH is not set
@ -1721,6 +1778,8 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DEBUG_MUTEXES is not set
# CONFIG_DEBUG_LOCK_ALLOC is not set
@ -1744,12 +1803,16 @@ CONFIG_DEBUG_INFO=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TRACEHOOK_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_LKDTM is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_DYNAMIC_DEBUG is not set
@ -1778,6 +1841,7 @@ CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
# CONFIG_BFIN_ISRAM_SELF_TEST is not set
# CONFIG_BFIN_PSEUDODBG_INSNS is not set
#
# Security options
@ -1785,7 +1849,11 @@ CONFIG_ACCESS_CHECK=y
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y
#

1
arch/blackfin/configs/BF561-ACVILON_defconfig
View file

@ -330,7 +330,6 @@ CONFIG_SYS_BFIN_SPINLOCK_L1=y
CONFIG_CACHELINE_ALIGNED_L1=y
# CONFIG_SYSCALL_TAB_L1 is not set
# CONFIG_CPLB_SWITCH_TAB_L1 is not set
CONFIG_APP_STACK_L1=y
#
# Speed Optimizations

85
arch/blackfin/configs/BF561-EZKIT_defconfig
View file

@ -1,7 +1,8 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32.2
# Linux kernel version: 2.6.34
#
CONFIG_SYMBOL_PREFIX="_"
# CONFIG_MMU is not set
# CONFIG_FPU is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
@ -49,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_TINY_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
@ -56,8 +59,6 @@ CONFIG_RCU_FANOUT=32
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
@ -66,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
@ -98,6 +100,7 @@ CONFIG_SLAB=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
#
# GCOV-based kernel profiling
@ -122,14 +125,41 @@ CONFIG_BLOCK=y
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
@ -293,8 +323,16 @@ CONFIG_HZ=250
CONFIG_SCHED_HRTICK=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
#
# Clock event device
#
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
#
# Clock souce
#
CONFIG_CYCLES_CLOCKSOURCE=y
# CONFIG_GPTMR0_CLOCKSOURCE is not set
CONFIG_TICK_ONESHOT=y
@ -326,12 +364,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
CONFIG_ACCESS_OK_L1=y
CONFIG_MEMSET_L1=y
CONFIG_MEMCPY_L1=y
CONFIG_STRCMP_L1=y
CONFIG_STRNCMP_L1=y
CONFIG_STRCPY_L1=y
CONFIG_STRNCPY_L1=y
CONFIG_SYS_BFIN_SPINLOCK_L1=y
# CONFIG_IP_CHECKSUM_L1 is not set
CONFIG_CACHELINE_ALIGNED_L1=y
# CONFIG_SYSCALL_TAB_L1 is not set
# CONFIG_CPLB_SWITCH_TAB_L1 is not set
CONFIG_APP_STACK_L1=y
CONFIG_CACHE_FLUSH_L1=y
#
# Speed Optimizations
@ -439,7 +481,6 @@ CONFIG_NET=y
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
@ -643,6 +684,10 @@ CONFIG_MTD_PHYSMAP=m
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
@ -652,7 +697,9 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_BLK_DEV_HD is not set
CONFIG_MISC_DEVICES=y
# CONFIG_AD525X_DPOT is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_C2PORT is not set
#
@ -666,6 +713,7 @@ CONFIG_HAVE_IDE=y
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
@ -722,6 +770,7 @@ CONFIG_SMC91X=y
CONFIG_INPUT=m
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
#
# Userland interfaces
@ -779,6 +828,7 @@ CONFIG_SERIAL_BFIN_UART0=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_BFIN_SPORT is not set
# CONFIG_SERIAL_TIMBERDALE is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
@ -800,6 +850,8 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_BFIN_SPORT is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set
#
# SPI Protocol Masters
@ -819,6 +871,7 @@ CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
# CONFIG_GPIO_IT8761E is not set
#
# I2C GPIO expanders:
@ -866,6 +919,7 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_AB4500_CORE is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
@ -978,6 +1032,7 @@ CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_LOGFS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
@ -1002,6 +1057,7 @@ CONFIG_SUNRPC=m
# CONFIG_RPCSEC_GSS_SPKM3 is not set
CONFIG_SMB_FS=m
# CONFIG_SMB_NLS_DEFAULT is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
@ -1103,12 +1159,16 @@ CONFIG_DEBUG_INFO=y
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_TRACEHOOK_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_LKDTM is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_DYNAMIC_DEBUG is not set
@ -1137,6 +1197,7 @@ CONFIG_EARLY_PRINTK=y
CONFIG_CPLB_INFO=y
CONFIG_ACCESS_CHECK=y
# CONFIG_BFIN_ISRAM_SELF_TEST is not set
# CONFIG_BFIN_PSEUDODBG_INSNS is not set
#
# Security options
@ -1144,7 +1205,11 @@ CONFIG_ACCESS_CHECK=y
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y
#

1
arch/blackfin/configs/CM-BF527_defconfig
View file

@ -319,7 +319,6 @@ CONFIG_ACCESS_OK_L1=y
CONFIG_CACHELINE_ALIGNED_L1=y
# CONFIG_SYSCALL_TAB_L1 is not set
# CONFIG_CPLB_SWITCH_TAB_L1 is not set
CONFIG_APP_STACK_L1=y
#
# Speed Optimizations

1
arch/blackfin/configs/CM-BF533_defconfig
View file

@ -279,7 +279,6 @@ CONFIG_IP_CHECKSUM_L1=y
CONFIG_CACHELINE_ALIGNED_L1=y
CONFIG_SYSCALL_TAB_L1=y
CONFIG_CPLB_SWITCH_TAB_L1=y
CONFIG_APP_STACK_L1=y
#
# Speed Optimizations

1
arch/blackfin/configs/CM-BF537E_defconfig
View file

@ -288,7 +288,6 @@ CONFIG_IP_CHECKSUM_L1=y
CONFIG_CACHELINE_ALIGNED_L1=y
CONFIG_SYSCALL_TAB_L1=y
CONFIG_CPLB_SWITCH_TAB_L1=y
CONFIG_APP_STACK_L1=y
#
# Speed Optimizations

1
arch/blackfin/configs/CM-BF537U_defconfig
View file

@ -288,7 +288,6 @@ CONFIG_IP_CHECKSUM_L1=y
CONFIG_CACHELINE_ALIGNED_L1=y
CONFIG_SYSCALL_TAB_L1=y
CONFIG_CPLB_SWITCH_TAB_L1=y
CONFIG_APP_STACK_L1=y
#
# Speed Optimizations

1
arch/blackfin/configs/CM-BF548_defconfig
View file

@ -346,7 +346,6 @@ CONFIG_ACCESS_OK_L1=y
CONFIG_CACHELINE_ALIGNED_L1=y
# CONFIG_SYSCALL_TAB_L1 is not set
# CONFIG_CPLB_SWITCH_TAB_L1 is not set
CONFIG_APP_STACK_L1=y
#
# Speed Optimizations

1
arch/blackfin/configs/CM-BF561_defconfig
View file

@ -318,7 +318,6 @@ CONFIG_IP_CHECKSUM_L1=y
CONFIG_CACHELINE_ALIGNED_L1=y
CONFIG_SYSCALL_TAB_L1=y
CONFIG_CPLB_SWITCH_TAB_L1=y
CONFIG_APP_STACK_L1=y
#
# Speed Optimizations

123
arch/blackfin/configs/PNAV-10_defconfig
View file

@ -1,7 +1,8 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32.2
# Linux kernel version: 2.6.34
#
CONFIG_SYMBOL_PREFIX="_"
# CONFIG_MMU is not set
# CONFIG_FPU is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
@ -37,6 +38,7 @@ CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_BZIP2 is not set
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
@ -49,13 +51,13 @@ CONFIG_SYSVIPC_SYSCTL=y
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_TINY_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_GROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
@ -92,6 +94,7 @@ CONFIG_SLAB=y
CONFIG_MMAP_ALLOW_UNINITIALIZED=y
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
#
# GCOV-based kernel profiling
@ -99,6 +102,7 @@ CONFIG_HAVE_OPROFILE=y
# CONFIG_SLOW_WORK is not set
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
@ -115,14 +119,41 @@ CONFIG_BLOCK=y
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
CONFIG_DEFAULT_IOSCHED="cfq"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
@ -255,8 +286,16 @@ CONFIG_HZ=250
# CONFIG_SCHED_HRTICK is not set
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
#
# Clock event device
#
# CONFIG_TICKSOURCE_GPTMR0 is not set
CONFIG_TICKSOURCE_CORETMR=y
#
# Clock souce
#
# CONFIG_CYCLES_CLOCKSOURCE is not set
# CONFIG_GPTMR0_CLOCKSOURCE is not set
# CONFIG_NO_HZ is not set
@ -287,12 +326,16 @@ CONFIG_ARITHMETIC_OPS_L1=y
CONFIG_ACCESS_OK_L1=y
CONFIG_MEMSET_L1=y
CONFIG_MEMCPY_L1=y
CONFIG_STRCMP_L1=y
CONFIG_STRNCMP_L1=y
CONFIG_STRCPY_L1=y
CONFIG_STRNCPY_L1=y
CONFIG_SYS_BFIN_SPINLOCK_L1=y
CONFIG_IP_CHECKSUM_L1=y
CONFIG_CACHELINE_ALIGNED_L1=y
CONFIG_SYSCALL_TAB_L1=y
CONFIG_CPLB_SWITCH_TAB_L1=y
CONFIG_APP_STACK_L1=y
CONFIG_CACHE_FLUSH_L1=y
#
# Speed Optimizations
@ -392,7 +435,6 @@ CONFIG_NET=y
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
@ -562,6 +604,10 @@ CONFIG_MTD_NAND_IDS=y
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
@ -575,6 +621,9 @@ CONFIG_MISC_DEVICES=y
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_ISL29003 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_DS1682 is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_C2PORT is not set
#
@ -591,6 +640,7 @@ CONFIG_HAVE_IDE=y
#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
@ -622,6 +672,7 @@ CONFIG_PHYLIB=y
# CONFIG_NATIONAL_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
@ -630,7 +681,6 @@ CONFIG_BFIN_MAC=y
# CONFIG_BFIN_MAC_USE_L1 is not set
CONFIG_BFIN_TX_DESC_NUM=100
CONFIG_BFIN_RX_DESC_NUM=100
CONFIG_BFIN_MAC_RMII=y
# CONFIG_SMC91X is not set
# CONFIG_DM9000 is not set
# CONFIG_ENC28J60 is not set
@ -671,6 +721,7 @@ CONFIG_BFIN_MAC_RMII=y
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
#
# Userland interfaces
@ -690,9 +741,9 @@ CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_ADS7846 is not set
CONFIG_TOUCHSCREEN_AD7877=y
# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_AD7160 is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
@ -709,6 +760,7 @@ CONFIG_TOUCHSCREEN_AD7877=y
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ATI_REMOTE is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
@ -716,9 +768,8 @@ CONFIG_INPUT_MISC=y
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_AD714X is not set
# CONFIG_INPUT_ADXL34X is not set
# CONFIG_INPUT_PCF8574 is not set
# CONFIG_INPUT_ADXL34X is not set
#
# Hardware I/O ports
@ -761,6 +812,7 @@ CONFIG_SERIAL_BFIN_UART1=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_BFIN_SPORT is not set
# CONFIG_SERIAL_TIMBERDALE is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
@ -788,6 +840,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set
#
# External I2C/SMBus adapter drivers
@ -800,16 +853,9 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
@ -821,6 +867,8 @@ CONFIG_SPI_BFIN=y
# CONFIG_SPI_BFIN_SPORT is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_DESIGNWARE is not set
#
# SPI Protocol Masters
@ -852,10 +900,11 @@ CONFIG_HWMON=y
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7473 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
@ -867,6 +916,7 @@ CONFIG_HWMON=y
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
@ -892,6 +942,7 @@ CONFIG_HWMON=y
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
@ -905,6 +956,7 @@ CONFIG_HWMON=y
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_THERMAL is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
@ -918,19 +970,23 @@ CONFIG_SSB_POSSIBLE=y
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_AB3100_CORE is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_AB4500_CORE is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
@ -973,6 +1029,7 @@ CONFIG_FB_BF537_LQ035=y
# CONFIG_FB_BROADSHEET is not set
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
# CONFIG_LCD_L4F00242T03 is not set
# CONFIG_LCD_LMS283GF05 is not set
# CONFIG_LCD_LTV350QV is not set
# CONFIG_LCD_ILI9320 is not set
@ -981,6 +1038,7 @@ CONFIG_LCD_CLASS_DEVICE=y
# CONFIG_LCD_PLATFORM is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GENERIC=y
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
#
@ -1011,11 +1069,6 @@ CONFIG_SND_DRIVERS=y
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
CONFIG_SND_SPI=y
#
# ALSA Blackfin devices
#
# CONFIG_SND_BFIN_AD73322 is not set
# CONFIG_SND_SOC is not set
CONFIG_SOUND_PRIME=y
CONFIG_HID_SUPPORT=y
@ -1073,6 +1126,7 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
@ -1101,7 +1155,9 @@ CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
@ -1137,7 +1193,6 @@ CONFIG_FS_MBCACHE=y
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
@ -1186,6 +1241,7 @@ CONFIG_MISC_FILESYSTEMS=y
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_LOGFS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
@ -1210,6 +1266,7 @@ CONFIG_SUNRPC=m
# CONFIG_RPCSEC_GSS_SPKM3 is not set
CONFIG_SMB_FS=m
# CONFIG_SMB_NLS_DEFAULT is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
@ -1276,11 +1333,14 @@ CONFIG_FRAME_WARN=1024
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_SECTION_MISMATCH=y
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_BUGVERBOSE=y
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_TRACEHOOK_SELF_TEST is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_SAMPLES is not set
@ -1300,6 +1360,7 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
# CONFIG_CPLB_INFO is not set
# CONFIG_ACCESS_CHECK is not set
# CONFIG_BFIN_ISRAM_SELF_TEST is not set
# CONFIG_BFIN_PSEUDODBG_INSNS is not set
#
# Security options
@ -1309,8 +1370,12 @@ CONFIG_SECURITY=y
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_NETWORK is not set
# CONFIG_SECURITY_PATH is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
CONFIG_CRYPTO=y
#

1
arch/blackfin/configs/TCM-BF518_defconfig
View file

@ -333,7 +333,6 @@ CONFIG_ACCESS_OK_L1=y
CONFIG_CACHELINE_ALIGNED_L1=y
# CONFIG_SYSCALL_TAB_L1 is not set
# CONFIG_CPLB_SWITCH_TAB_L1 is not set
CONFIG_APP_STACK_L1=y
#
# Speed Optimizations

1
arch/blackfin/configs/TCM-BF537_defconfig
View file

@ -287,7 +287,6 @@ CONFIG_IP_CHECKSUM_L1=y
CONFIG_CACHELINE_ALIGNED_L1=y
CONFIG_SYSCALL_TAB_L1=y
CONFIG_CPLB_SWITCH_TAB_L1=y
CONFIG_APP_STACK_L1=y
#
# Speed Optimizations

74
arch/blackfin/include/asm/bfin_rotary.h
View file

@ -2,7 +2,7 @@
* board initialization should put one of these structures into platform_data
* and place the bfin-rotary onto platform_bus named "bfin-rotary".
*
* Copyright 2008 Analog Devices Inc.
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
@ -40,4 +40,76 @@ struct bfin_rotary_platform_data {
unsigned short debounce; /* 0..17 */
unsigned short mode;
};
/* CNT_CONFIG bitmasks */
#define CNTE (1 << 0) /* Counter Enable */
#define DEBE (1 << 1) /* Debounce Enable */
#define CDGINV (1 << 4) /* CDG Pin Polarity Invert */
#define CUDINV (1 << 5) /* CUD Pin Polarity Invert */
#define CZMINV (1 << 6) /* CZM Pin Polarity Invert */
#define CNTMODE_SHIFT 8
#define CNTMODE (0x7 << CNTMODE_SHIFT) /* Counter Operating Mode */
#define ZMZC (1 << 1) /* CZM Zeroes Counter Enable */
#define BNDMODE_SHIFT 12
#define BNDMODE (0x3 << BNDMODE_SHIFT) /* Boundary register Mode */
#define INPDIS (1 << 15) /* CUG and CDG Input Disable */
#define CNTMODE_QUADENC (0 << CNTMODE_SHIFT) /* quadrature encoder mode */
#define CNTMODE_BINENC (1 << CNTMODE_SHIFT) /* binary encoder mode */
#define CNTMODE_UDCNT (2 << CNTMODE_SHIFT) /* up/down counter mode */
#define CNTMODE_DIRCNT (4 << CNTMODE_SHIFT) /* direction counter mode */
#define CNTMODE_DIRTMR (5 << CNTMODE_SHIFT) /* direction timer mode */
#define BNDMODE_COMP (0 << BNDMODE_SHIFT) /* boundary compare mode */
#define BNDMODE_ZERO (1 << BNDMODE_SHIFT) /* boundary compare and zero mode */
#define BNDMODE_CAPT (2 << BNDMODE_SHIFT) /* boundary capture mode */
#define BNDMODE_AEXT (3 << BNDMODE_SHIFT) /* boundary auto-extend mode */
/* CNT_IMASK bitmasks */
#define ICIE (1 << 0) /* Illegal Gray/Binary Code Interrupt Enable */
#define UCIE (1 << 1) /* Up count Interrupt Enable */
#define DCIE (1 << 2) /* Down count Interrupt Enable */
#define MINCIE (1 << 3) /* Min Count Interrupt Enable */
#define MAXCIE (1 << 4) /* Max Count Interrupt Enable */
#define COV31IE (1 << 5) /* Bit 31 Overflow Interrupt Enable */
#define COV15IE (1 << 6) /* Bit 15 Overflow Interrupt Enable */
#define CZEROIE (1 << 7) /* Count to Zero Interrupt Enable */
#define CZMIE (1 << 8) /* CZM Pin Interrupt Enable */
#define CZMEIE (1 << 9) /* CZM Error Interrupt Enable */
#define CZMZIE (1 << 10) /* CZM Zeroes Counter Interrupt Enable */
/* CNT_STATUS bitmasks */
#define ICII (1 << 0) /* Illegal Gray/Binary Code Interrupt Identifier */
#define UCII (1 << 1) /* Up count Interrupt Identifier */
#define DCII (1 << 2) /* Down count Interrupt Identifier */
#define MINCII (1 << 3) /* Min Count Interrupt Identifier */
#define MAXCII (1 << 4) /* Max Count Interrupt Identifier */
#define COV31II (1 << 5) /* Bit 31 Overflow Interrupt Identifier */
#define COV15II (1 << 6) /* Bit 15 Overflow Interrupt Identifier */
#define CZEROII (1 << 7) /* Count to Zero Interrupt Identifier */
#define CZMII (1 << 8) /* CZM Pin Interrupt Identifier */
#define CZMEII (1 << 9) /* CZM Error Interrupt Identifier */
#define CZMZII (1 << 10) /* CZM Zeroes Counter Interrupt Identifier */
/* CNT_COMMAND bitmasks */
#define W1LCNT 0xf /* Load Counter Register */
#define W1LMIN 0xf0 /* Load Min Register */
#define W1LMAX 0xf00 /* Load Max Register */
#define W1ZMONCE (1 << 12) /* Enable CZM Clear Counter Once */
#define W1LCNT_ZERO (1 << 0) /* write 1 to load CNT_COUNTER with zero */
#define W1LCNT_MIN (1 << 2) /* write 1 to load CNT_COUNTER from CNT_MIN */
#define W1LCNT_MAX (1 << 3) /* write 1 to load CNT_COUNTER from CNT_MAX */
#define W1LMIN_ZERO (1 << 4) /* write 1 to load CNT_MIN with zero */
#define W1LMIN_CNT (1 << 5) /* write 1 to load CNT_MIN from CNT_COUNTER */
#define W1LMIN_MAX (1 << 7) /* write 1 to load CNT_MIN from CNT_MAX */
#define W1LMAX_ZERO (1 << 8) /* write 1 to load CNT_MAX with zero */
#define W1LMAX_CNT (1 << 9) /* write 1 to load CNT_MAX from CNT_COUNTER */
#define W1LMAX_MIN (1 << 10) /* write 1 to load CNT_MAX from CNT_MIN */
/* CNT_DEBOUNCE bitmasks */
#define DPRESCALE 0xf /* Load Counter Register */
#endif

119
arch/blackfin/include/asm/bfin_sdh.h
View file

@ -1,7 +1,7 @@
/*
* bfin_sdh.h - Blackfin SDH definitions
* Blackfin Secure Digital Host (SDH) definitions
*
* Copyright 2008 Analog Devices Inc.
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
@ -9,6 +9,7 @@
#ifndef __BFIN_SDH_H__
#define __BFIN_SDH_H__
/* Platform resources */
struct bfin_sd_host {
int dma_chan;
int irq_int0;
@ -16,4 +17,118 @@ struct bfin_sd_host {
u16 pin_req[7];
};
/* SDH_COMMAND bitmasks */
#define CMD_IDX 0x3f /* Command Index */
#define CMD_RSP (1 << 6) /* Response */
#define CMD_L_RSP (1 << 7) /* Long Response */
#define CMD_INT_E (1 << 8) /* Command Interrupt */
#define CMD_PEND_E (1 << 9) /* Command Pending */
#define CMD_E (1 << 10) /* Command Enable */
/* SDH_PWR_CTL bitmasks */
#define PWR_ON 0x3 /* Power On */
#define SD_CMD_OD (1 << 6) /* Open Drain Output */
#define ROD_CTL (1 << 7) /* Rod Control */
/* SDH_CLK_CTL bitmasks */
#define CLKDIV 0xff /* MC_CLK Divisor */
#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */
#define PWR_SV_E (1 << 9) /* Power Save Enable */
#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */
#define WIDE_BUS (1 << 11) /* Wide Bus Mode Enable */
/* SDH_RESP_CMD bitmasks */
#define RESP_CMD 0x3f /* Response Command */
/* SDH_DATA_CTL bitmasks */
#define DTX_E (1 << 0) /* Data Transfer Enable */
#define DTX_DIR (1 << 1) /* Data Transfer Direction */
#define DTX_MODE (1 << 2) /* Data Transfer Mode */
#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */
#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */
/* SDH_STATUS bitmasks */
#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */
#define DAT_CRC_FAIL (1 << 1) /* Data CRC Fail */
#define CMD_TIME_OUT (1 << 2) /* CMD Time Out */
#define DAT_TIME_OUT (1 << 3) /* Data Time Out */
#define TX_UNDERRUN (1 << 4) /* Transmit Underrun */
#define RX_OVERRUN (1 << 5) /* Receive Overrun */
#define CMD_RESP_END (1 << 6) /* CMD Response End */
#define CMD_SENT (1 << 7) /* CMD Sent */
#define DAT_END (1 << 8) /* Data End */
#define START_BIT_ERR (1 << 9) /* Start Bit Error */
#define DAT_BLK_END (1 << 10) /* Data Block End */
#define CMD_ACT (1 << 11) /* CMD Active */
#define TX_ACT (1 << 12) /* Transmit Active */
#define RX_ACT (1 << 13) /* Receive Active */
#define TX_FIFO_STAT (1 << 14) /* Transmit FIFO Status */
#define RX_FIFO_STAT (1 << 15) /* Receive FIFO Status */
#define TX_FIFO_FULL (1 << 16) /* Transmit FIFO Full */
#define RX_FIFO_FULL (1 << 17) /* Receive FIFO Full */
#define TX_FIFO_ZERO (1 << 18) /* Transmit FIFO Empty */
#define RX_DAT_ZERO (1 << 19) /* Receive FIFO Empty */
#define TX_DAT_RDY (1 << 20) /* Transmit Data Available */
#define RX_FIFO_RDY (1 << 21) /* Receive Data Available */
/* SDH_STATUS_CLR bitmasks */
#define CMD_CRC_FAIL_STAT (1 << 0) /* CMD CRC Fail Status */
#define DAT_CRC_FAIL_STAT (1 << 1) /* Data CRC Fail Status */
#define CMD_TIMEOUT_STAT (1 << 2) /* CMD Time Out Status */
#define DAT_TIMEOUT_STAT (1 << 3) /* Data Time Out status */
#define TX_UNDERRUN_STAT (1 << 4) /* Transmit Underrun Status */
#define RX_OVERRUN_STAT (1 << 5) /* Receive Overrun Status */
#define CMD_RESP_END_STAT (1 << 6) /* CMD Response End Status */
#define CMD_SENT_STAT (1 << 7) /* CMD Sent Status */
#define DAT_END_STAT (1 << 8) /* Data End Status */
#define START_BIT_ERR_STAT (1 << 9) /* Start Bit Error Status */
#define DAT_BLK_END_STAT (1 << 10) /* Data Block End Status */
/* SDH_MASK0 bitmasks */
#define CMD_CRC_FAIL_MASK (1 << 0) /* CMD CRC Fail Mask */
#define DAT_CRC_FAIL_MASK (1 << 1) /* Data CRC Fail Mask */
#define CMD_TIMEOUT_MASK (1 << 2) /* CMD Time Out Mask */
#define DAT_TIMEOUT_MASK (1 << 3) /* Data Time Out Mask */
#define TX_UNDERRUN_MASK (1 << 4) /* Transmit Underrun Mask */
#define RX_OVERRUN_MASK (1 << 5) /* Receive Overrun Mask */
#define CMD_RESP_END_MASK (1 << 6) /* CMD Response End Mask */
#define CMD_SENT_MASK (1 << 7) /* CMD Sent Mask */
#define DAT_END_MASK (1 << 8) /* Data End Mask */
#define START_BIT_ERR_MASK (1 << 9) /* Start Bit Error Mask */
#define DAT_BLK_END_MASK (1 << 10) /* Data Block End Mask */
#define CMD_ACT_MASK (1 << 11) /* CMD Active Mask */
#define TX_ACT_MASK (1 << 12) /* Transmit Active Mask */
#define RX_ACT_MASK (1 << 13) /* Receive Active Mask */
#define TX_FIFO_STAT_MASK (1 << 14) /* Transmit FIFO Status Mask */
#define RX_FIFO_STAT_MASK (1 << 15) /* Receive FIFO Status Mask */
#define TX_FIFO_FULL_MASK (1 << 16) /* Transmit FIFO Full Mask */
#define RX_FIFO_FULL_MASK (1 << 17) /* Receive FIFO Full Mask */
#define TX_FIFO_ZERO_MASK (1 << 18) /* Transmit FIFO Empty Mask */
#define RX_DAT_ZERO_MASK (1 << 19) /* Receive FIFO Empty Mask */
#define TX_DAT_RDY_MASK (1 << 20) /* Transmit Data Available Mask */
#define RX_FIFO_RDY_MASK (1 << 21) /* Receive Data Available Mask */
/* SDH_FIFO_CNT bitmasks */
#define FIFO_COUNT 0x7fff /* FIFO Count */
/* SDH_E_STATUS bitmasks */
#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */
#define SD_CARD_DET (1 << 4) /* SD Card Detect */
/* SDH_E_MASK bitmasks */
#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */
#define SCD_MSK (1 << 6) /* Mask Card Detect */
/* SDH_CFG bitmasks */
#define CLKS_EN (1 << 0) /* Clocks Enable */
#define SD4E (1 << 2) /* SDIO 4-Bit Enable */
#define MWE (1 << 3) /* Moving Window Enable */
#define SD_RST (1 << 4) /* SDMMC Reset */
#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */
#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */
#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */
/* SDH_RD_WAIT_EN bitmasks */
#define RWR (1 << 0) /* Read Wait Request */
#endif

2
arch/blackfin/include/asm/bitops.h
View file

@ -119,7 +119,7 @@ static inline unsigned int hweight32(unsigned int w)
{
unsigned int res;
__asm__ ("%0.l = ONES %0;"
__asm__ ("%0.l = ONES %1;"
"%0 = %0.l (Z);"
: "=d" (res) : "d" (w));
return res;

8
arch/blackfin/include/asm/cdef_LPBlackfin.h
View file

@ -216,12 +216,16 @@
#define bfin_write_EVT14(val) bfin_write32(EVT14,val)
#define bfin_read_EVT15() bfin_read32(EVT15)
#define bfin_write_EVT15(val) bfin_write32(EVT15,val)
#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE,val)
#define bfin_read_IMASK() bfin_read32(IMASK)
#define bfin_write_IMASK(val) bfin_write32(IMASK,val)
#define bfin_read_IPEND() bfin_read32(IPEND)
#define bfin_write_IPEND(val) bfin_write32(IPEND,val)
#define bfin_read_ILAT() bfin_read32(ILAT)
#define bfin_write_ILAT(val) bfin_write32(ILAT,val)
#define bfin_read_IPRIO() bfin_read32(IPRIO)
#define bfin_write_IPRIO(val) bfin_write32(IPRIO,val)
/*Core Timer Registers*/
#define bfin_read_TCNTL() bfin_read32(TCNTL)
@ -299,8 +303,4 @@
#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1)
#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1,val)
/*
#define IPRIO 0xFFE02110
*/
#endif /* _CDEF_LPBLACKFIN_H */

18
arch/blackfin/include/asm/def_LPBlackfin.h
View file

@ -50,6 +50,23 @@
#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32, )
#define bfin_read(addr) \
({ \
sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
({ BUG(); 0; }); \
})
#define bfin_write(addr, val) \
({ \
switch (sizeof(*(addr))) { \
case 1: bfin_write8(addr, val); break; \
case 2: bfin_write16(addr, val); break; \
case 4: bfin_write32(addr, val); break; \
default: BUG(); \
} \
})
#endif /* __ASSEMBLY__ */
/**************************************************
@ -377,6 +394,7 @@
#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
#define EVT_OVERRIDE 0xFFE02100 /* Event Vector Override Register */
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define ILAT 0xFFE0210C /* Interrupt Latch Register */

1
arch/blackfin/include/asm/dma.h
View file

@ -276,6 +276,7 @@ static inline void clear_dma_irqstat(unsigned int channel)
}
void *dma_memcpy(void *dest, const void *src, size_t count);
void *dma_memcpy_nocache(void *dest, const void *src, size_t count);
void *safe_dma_memcpy(void *dest, const void *src, size_t count);
void blackfin_dma_early_init(void);
void early_dma_memcpy(void *dest, const void *src, size_t count);

1
arch/blackfin/include/asm/elf.h
View file

@ -119,6 +119,7 @@ do { \
#define ELF_CORE_COPY_REGS(pr_reg, regs) \
memcpy((char *) &pr_reg, (char *)regs, \
sizeof(struct pt_regs));
#define ELF_CORE_COPY_FPREGS(...) 0 /* Blackfin has no FPU */
/* This yields a mask that user programs can use to figure out what
instruction set this cpu supports. */

16
arch/blackfin/include/asm/ftrace.h
View file

@ -12,6 +12,22 @@
#ifndef __ASSEMBLY__
#ifdef CONFIG_DYNAMIC_FTRACE
extern void _mcount(void);
#define MCOUNT_ADDR ((unsigned long)_mcount)
static inline unsigned long ftrace_call_adjust(unsigned long addr)
{
return addr;
}
struct dyn_arch_ftrace {
/* No extra data needed for Blackfin */
};
#endif
#ifdef CONFIG_FRAME_POINTER
#include <linux/mm.h>

111
arch/blackfin/include/asm/gpio.h
View file

@ -7,63 +7,63 @@
#ifndef __ARCH_BLACKFIN_GPIO_H__
#define __ARCH_BLACKFIN_GPIO_H__
#define gpio_bank(x) ((x) >> 4)
#define gpio_bit(x) (1<<((x) & 0xF))
#define gpio_sub_n(x) ((x) & 0xF)
#define gpio_bank(x) ((x) >> 4)
#define gpio_bit(x) (1<<((x) & 0xF))
#define gpio_sub_n(x) ((x) & 0xF)
#define GPIO_BANKSIZE 16
#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE)
#define GPIO_BANKSIZE 16
#define GPIO_BANK_NUM DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE)
#include <mach/gpio.h>
#define GPIO_0 0
#define GPIO_1 1
#define GPIO_2 2
#define GPIO_3 3
#define GPIO_4 4
#define GPIO_5 5
#define GPIO_6 6
#define GPIO_7 7
#define GPIO_8 8
#define GPIO_9 9
#define GPIO_10 10
#define GPIO_11 11
#define GPIO_12 12
#define GPIO_13 13
#define GPIO_14 14
#define GPIO_15 15
#define GPIO_16 16
#define GPIO_17 17
#define GPIO_18 18
#define GPIO_19 19
#define GPIO_20 20
#define GPIO_21 21
#define GPIO_22 22
#define GPIO_23 23
#define GPIO_24 24
#define GPIO_25 25
#define GPIO_26 26
#define GPIO_27 27
#define GPIO_28 28
#define GPIO_29 29
#define GPIO_30 30
#define GPIO_31 31
#define GPIO_32 32
#define GPIO_33 33
#define GPIO_34 34
#define GPIO_35 35
#define GPIO_36 36
#define GPIO_37 37
#define GPIO_38 38
#define GPIO_39 39
#define GPIO_40 40
#define GPIO_41 41
#define GPIO_42 42
#define GPIO_43 43
#define GPIO_44 44
#define GPIO_45 45
#define GPIO_46 46
#define GPIO_47 47
#define GPIO_0 0
#define GPIO_1 1
#define GPIO_2 2
#define GPIO_3 3
#define GPIO_4 4
#define GPIO_5 5
#define GPIO_6 6
#define GPIO_7 7
#define GPIO_8 8
#define GPIO_9 9
#define GPIO_10 10
#define GPIO_11 11
#define GPIO_12 12
#define GPIO_13 13
#define GPIO_14 14
#define GPIO_15 15
#define GPIO_16 16
#define GPIO_17 17
#define GPIO_18 18
#define GPIO_19 19
#define GPIO_20 20
#define GPIO_21 21
#define GPIO_22 22
#define GPIO_23 23
#define GPIO_24 24
#define GPIO_25 25
#define GPIO_26 26
#define GPIO_27 27
#define GPIO_28 28
#define GPIO_29 29
#define GPIO_30 30
#define GPIO_31 31
#define GPIO_32 32
#define GPIO_33 33
#define GPIO_34 34
#define GPIO_35 35
#define GPIO_36 36
#define GPIO_37 37
#define GPIO_38 38
#define GPIO_39 39
#define GPIO_40 40
#define GPIO_41 41
#define GPIO_42 42
#define GPIO_43 43
#define GPIO_44 44
#define GPIO_45 45
#define GPIO_46 46
#define GPIO_47 47
#define PERIPHERAL_USAGE 1
#define GPIO_USAGE 0
@ -279,6 +279,11 @@ static inline int gpio_direction_output(unsigned gpio, int value)
return bfin_gpio_direction_output(gpio, value);
}
static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
{
return -EINVAL;
}
static inline int gpio_get_value(unsigned gpio)
{
return bfin_gpio_get_value(gpio);

8
arch/blackfin/include/asm/io.h
View file

@ -124,7 +124,13 @@ static inline unsigned int readl(const volatile void __iomem *addr)
#define iowrite16(val, x) writew(val, x)
#define iowrite32(val, x) writel(val, x)
#define mmiowb() wmb()
/**
* I/O write barrier
*
* Ensure ordering of I/O space writes. This will make sure that writes
* following the barrier will arrive after all previous writes.
*/
#define mmiowb() do { SSYNC(); wmb(); } while (0)
#define IO_SPACE_LIMIT 0xffffffff

18
arch/blackfin/include/asm/mem_init.h
View file

@ -10,7 +10,6 @@
#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
defined(CONFIG_MEM_GENERIC_BOARD) || \
defined(CONFIG_MEM_MT48LC32M8A2_75) || \
defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
@ -178,7 +177,6 @@
#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
defined(CONFIG_MEM_GENERIC_BOARD) || \
defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
defined(CONFIG_MEM_MT48LC32M8A2_75)
@ -248,22 +246,6 @@
#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
#endif
#if defined(CONFIG_MEM_GENERIC_BOARD)
#define DDR_SIZE DEVSZ_512
#define DDR_WIDTH DEVWD_16
#define DDR_MAX_tCK 13
#define DDR_tRCD DDR_TRCD(3)
#define DDR_tWTR DDR_TWTR(2)
#define DDR_tWR DDR_TWR(2)
#define DDR_tMRD DDR_TMRD(2)
#define DDR_tRP DDR_TRP(3)
#define DDR_tRAS DDR_TRAS(7)
#define DDR_tRC DDR_TRC(10)
#define DDR_tRFC DDR_TRFC(12)
#define DDR_tREFI DDR_TREFI(1288)
#endif
#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
#elif(CONFIG_SCLK_HZ <= 133333333)

10
arch/blackfin/include/asm/portmux.h
View file

@ -1,9 +1,9 @@
/*
* Common header file for Blackfin family of processors
*
 * Copyright 2007-2008 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
* Copyright 2007-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _PORTMUX_H_
@ -1042,8 +1042,8 @@ void peripheral_free_list(const unsigned short per[]);
#define P_NOR_CLK P_UNDEF
#endif
#ifndef P_TMRCLK
#define P_TMRCLK P_UNDEF
#ifndef P_TMRCLK
#define P_TMRCLK P_UNDEF
#endif
#ifndef P_AMC_ARDY_NOR_WAIT

1
arch/blackfin/kernel/Makefile
View file

@ -16,6 +16,7 @@ else
obj-y += time.o
endif
obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
obj-$(CONFIG_FUNCTION_TRACER) += ftrace-entry.o
obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
CFLAGS_REMOVE_ftrace.o = -pg

19
arch/blackfin/kernel/bfin_dma_5xx.c
View file

@ -450,7 +450,6 @@ void *dma_memcpy(void *pdst, const void *psrc, size_t size)
{
unsigned long dst = (unsigned long)pdst;
unsigned long src = (unsigned long)psrc;
size_t bulk, rest;
if (bfin_addr_dcacheable(src))
blackfin_dcache_flush_range(src, src + size);
@ -458,6 +457,22 @@ void *dma_memcpy(void *pdst, const void *psrc, size_t size)
if (bfin_addr_dcacheable(dst))
blackfin_dcache_invalidate_range(dst, dst + size);
return dma_memcpy_nocache(pdst, psrc, size);
}
EXPORT_SYMBOL(dma_memcpy);
/**
* dma_memcpy_nocache - DMA memcpy under mutex lock
* - No cache flush/invalidate
*
* Do not check arguments before starting the DMA memcpy. Break the transfer
* up into two pieces. The first transfer is in multiples of 64k and the
* second transfer is the piece smaller than 64k.
*/
void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
{
size_t bulk, rest;
bulk = size & ~0xffff;
rest = size - bulk;
if (bulk)
@ -465,7 +480,7 @@ void *dma_memcpy(void *pdst, const void *psrc, size_t size)
_dma_memcpy(pdst + bulk, psrc + bulk, rest);
return pdst;
}
EXPORT_SYMBOL(dma_memcpy);
EXPORT_SYMBOL(dma_memcpy_nocache);
/**
* safe_dma_memcpy - DMA memcpy w/argument checking

111
arch/blackfin/kernel/bfin_gpio.c
View file

@ -108,11 +108,7 @@ static unsigned short * const port_fer[] = {
};
#endif
static unsigned short reserved_gpio_map[GPIO_BANK_NUM];
static unsigned short reserved_peri_map[gpio_bank(MAX_RESOURCES)];
static unsigned short reserved_gpio_irq_map[GPIO_BANK_NUM];
#define RESOURCE_LABEL_SIZE 16
#define RESOURCE_LABEL_SIZE 16
static struct str_ident {
char name[RESOURCE_LABEL_SIZE];
@ -122,19 +118,6 @@ static struct str_ident {
static struct gpio_port_s gpio_bank_saved[GPIO_BANK_NUM];
#endif
inline int check_gpio(unsigned gpio)
{
#if defined(CONFIG_BF54x)
if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
|| gpio == GPIO_PH14 || gpio == GPIO_PH15
|| gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
return -EINVAL;
#endif
if (gpio >= MAX_BLACKFIN_GPIOS)
return -EINVAL;
return 0;
}
static void gpio_error(unsigned gpio)
{
printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
@ -167,6 +150,29 @@ static int cmp_label(unsigned short ident, const char *label)
return -EINVAL;
}
#define map_entry(m, i) reserved_##m##_map[gpio_bank(i)]
#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i))
#define reserve(m, i) (map_entry(m, i) |= gpio_bit(i))
#define unreserve(m, i) (map_entry(m, i) &= ~gpio_bit(i))
#define DECLARE_RESERVED_MAP(m, c) static unsigned short reserved_##m##_map[c]
DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM);
DECLARE_RESERVED_MAP(peri, DIV_ROUND_UP(MAX_RESOURCES, GPIO_BANKSIZE));
DECLARE_RESERVED_MAP(gpio_irq, GPIO_BANK_NUM);
inline int check_gpio(unsigned gpio)
{
#if defined(CONFIG_BF54x)
if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
|| gpio == GPIO_PH14 || gpio == GPIO_PH15
|| gpio == GPIO_PJ14 || gpio == GPIO_PJ15)
return -EINVAL;
#endif
if (gpio >= MAX_BLACKFIN_GPIOS)
return -EINVAL;
return 0;
}
static void port_setup(unsigned gpio, unsigned short usage)
{
#if defined(BF538_FAMILY)
@ -475,7 +481,7 @@ GET_GPIO_P(maskb)
#ifdef CONFIG_PM
static unsigned short wakeup_map[GPIO_BANK_NUM];
DECLARE_RESERVED_MAP(wakeup, GPIO_BANK_NUM);
static const unsigned int sic_iwr_irqs[] = {
#if defined(BF533_FAMILY)
@ -521,9 +527,9 @@ int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
local_irq_save_hw(flags);
if (ctrl)
wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
reserve(wakeup, gpio);
else
wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
unreserve(wakeup, gpio);
set_gpio_maskb(gpio, ctrl);
local_irq_restore_hw(flags);
@ -536,7 +542,7 @@ int bfin_pm_standby_ctrl(unsigned ctrl)
u16 bank, mask, i;
for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
mask = wakeup_map[gpio_bank(i)];
mask = map_entry(wakeup, i);
bank = gpio_bank(i);
if (mask)
@ -653,7 +659,7 @@ EXPORT_SYMBOL(get_gpio_dir);
/***********************************************************
*
* FUNCTIONS: Blackfin Peripheral Resource Allocation
* FUNCTIONS: Blackfin Peripheral Resource Allocation
* and PortMux Setup
*
* INPUTS/OUTPUTS:
@ -689,8 +695,7 @@ int peripheral_request(unsigned short per, const char *label)
/* If a pin can be muxed as either GPIO or peripheral, make
* sure it is not already a GPIO pin when we request it.
*/
if (unlikely(!check_gpio(ident) &&
reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) {
if (system_state == SYSTEM_BOOTING)
dump_stack();
printk(KERN_ERR
@ -700,7 +705,7 @@ int peripheral_request(unsigned short per, const char *label)
return -EBUSY;
}
if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
if (unlikely(is_reserved(peri, ident, 1))) {
/*
* Pin functions like AMC address strobes my
@ -731,7 +736,7 @@ int peripheral_request(unsigned short per, const char *label)
}
anyway:
reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
reserve(peri, ident);
portmux_setup(per);
port_setup(ident, PERIPHERAL_USAGE);
@ -777,7 +782,7 @@ void peripheral_free(unsigned short per)
local_irq_save_hw(flags);
if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
if (unlikely(!is_reserved(peri, ident, 0))) {
local_irq_restore_hw(flags);
return;
}
@ -785,7 +790,7 @@ void peripheral_free(unsigned short per)
if (!(per & P_MAYSHARE))
port_setup(ident, GPIO_USAGE);
reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
unreserve(peri, ident);
set_label(ident, "free");
@ -836,7 +841,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
return 0;
}
if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
if (unlikely(is_reserved(gpio, gpio, 1))) {
if (system_state == SYSTEM_BOOTING)
dump_stack();
printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
@ -844,7 +849,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
local_irq_restore_hw(flags);
return -EBUSY;
}
if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
if (unlikely(is_reserved(peri, gpio, 1))) {
if (system_state == SYSTEM_BOOTING)
dump_stack();
printk(KERN_ERR
@ -853,7 +858,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
local_irq_restore_hw(flags);
return -EBUSY;
}
if (unlikely(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
if (unlikely(is_reserved(gpio_irq, gpio, 1))) {
printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
" (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
}
@ -863,7 +868,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
}
#endif
reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
reserve(gpio, gpio);
set_label(gpio, label);
local_irq_restore_hw(flags);
@ -885,7 +890,7 @@ void bfin_gpio_free(unsigned gpio)
local_irq_save_hw(flags);
if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
if (unlikely(!is_reserved(gpio, gpio, 0))) {
if (system_state == SYSTEM_BOOTING)
dump_stack();
gpio_error(gpio);
@ -893,7 +898,7 @@ void bfin_gpio_free(unsigned gpio)
return;
}
reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
unreserve(gpio, gpio);
set_label(gpio, "free");
@ -902,7 +907,7 @@ void bfin_gpio_free(unsigned gpio)
EXPORT_SYMBOL(bfin_gpio_free);
#ifdef BFIN_SPECIAL_GPIO_BANKS
static unsigned short reserved_special_gpio_map[gpio_bank(MAX_RESOURCES)];
DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
int bfin_special_gpio_request(unsigned gpio, const char *label)
{
@ -921,14 +926,14 @@ int bfin_special_gpio_request(unsigned gpio, const char *label)
return 0;
}
if (unlikely(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
if (unlikely(is_reserved(special_gpio, gpio, 1))) {
local_irq_restore_hw(flags);
printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
gpio, get_label(gpio));
return -EBUSY;
}
if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
if (unlikely(is_reserved(peri, gpio, 1))) {
local_irq_restore_hw(flags);
printk(KERN_ERR
"bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
@ -937,8 +942,8 @@ int bfin_special_gpio_request(unsigned gpio, const char *label)
return -EBUSY;
}
reserved_special_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
reserved_peri_map[gpio_bank(gpio)] |= gpio_bit(gpio);
reserve(special_gpio, gpio);
reserve(peri, gpio);
set_label(gpio, label);
local_irq_restore_hw(flags);
@ -956,14 +961,14 @@ void bfin_special_gpio_free(unsigned gpio)
local_irq_save_hw(flags);
if (unlikely(!(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
if (unlikely(!is_reserved(special_gpio, gpio, 0))) {
gpio_error(gpio);
local_irq_restore_hw(flags);
return;
}
reserved_special_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
reserved_peri_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
unreserve(special_gpio, gpio);
unreserve(peri, gpio);
set_label(gpio, "free");
local_irq_restore_hw(flags);
}
@ -980,7 +985,7 @@ int bfin_gpio_irq_request(unsigned gpio, const char *label)
local_irq_save_hw(flags);
if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
if (unlikely(is_reserved(peri, gpio, 1))) {
if (system_state == SYSTEM_BOOTING)
dump_stack();
printk(KERN_ERR
@ -989,12 +994,12 @@ int bfin_gpio_irq_request(unsigned gpio, const char *label)
local_irq_restore_hw(flags);
return -EBUSY;
}
if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))
if (unlikely(is_reserved(gpio, gpio, 1)))
printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved by %s! "
"(Documentation/blackfin/bfin-gpio-notes.txt)\n",
gpio, get_label(gpio));
reserved_gpio_irq_map[gpio_bank(gpio)] |= gpio_bit(gpio);
reserve(gpio_irq, gpio);
set_label(gpio, label);
local_irq_restore_hw(flags);
@ -1013,7 +1018,7 @@ void bfin_gpio_irq_free(unsigned gpio)
local_irq_save_hw(flags);
if (unlikely(!(reserved_gpio_irq_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
if (unlikely(!is_reserved(gpio_irq, gpio, 0))) {
if (system_state == SYSTEM_BOOTING)
dump_stack();
gpio_error(gpio);
@ -1021,7 +1026,7 @@ void bfin_gpio_irq_free(unsigned gpio)
return;
}
reserved_gpio_irq_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
unreserve(gpio_irq, gpio);
set_label(gpio, "free");
@ -1042,7 +1047,7 @@ int bfin_gpio_direction_input(unsigned gpio)
{
unsigned long flags;
if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
if (unlikely(!is_reserved(gpio, gpio, 0))) {
gpio_error(gpio);
return -EINVAL;
}
@ -1084,7 +1089,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
{
unsigned long flags;
if (!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
if (unlikely(!is_reserved(gpio, gpio, 0))) {
gpio_error(gpio);
return -EINVAL;
}
@ -1153,13 +1158,13 @@ static int gpio_proc_read(char *buf, char **start, off_t offset,
int c, irq, gpio, outlen = 0;
for (c = 0; c < MAX_RESOURCES; c++) {
irq = reserved_gpio_irq_map[gpio_bank(c)] & gpio_bit(c);
gpio = reserved_gpio_map[gpio_bank(c)] & gpio_bit(c);
irq = is_reserved(gpio_irq, c, 1);
gpio = is_reserved(gpio, c, 1);
if (!check_gpio(c) && (gpio || irq))
len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
get_label(c), (gpio && irq) ? " *" : "",
get_gpio_dir(c) ? "OUTPUT" : "INPUT");
else if (reserved_peri_map[gpio_bank(c)] & gpio_bit(c))
else if (is_reserved(peri, c, 1))
len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
else
continue;

4
arch/blackfin/kernel/cplb-mpu/cplbinit.c
View file

@ -13,10 +13,6 @@
#include <asm/cplbinit.h>
#include <asm/mem_map.h>
#if ANOMALY_05000263
# error the MPU will not function safely while Anomaly 05000263 applies
#endif
struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];

87
arch/blackfin/kernel/ftrace-entry.S
View file

@ -10,6 +10,18 @@
.text
#ifdef CONFIG_DYNAMIC_FTRACE
/* Simple stub so we can boot the kernel until runtime patching has
* disabled all calls to this. Then it'll be unused.
*/
ENTRY(__mcount)
# if ANOMALY_05000371
nop; nop; nop; nop;
# endif
rts;
ENDPROC(__mcount)
/* GCC will have called us before setting up the function prologue, so we
* can clobber the normal scratch registers, but we need to make sure to
* save/restore the registers used for argument passing (R0-R2) in case
@ -20,15 +32,65 @@
* function. And since GCC pushed the previous RETS for us, the previous
* function will be waiting there. mmmm pie.
*/
ENTRY(__mcount)
#ifdef CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST
ENTRY(_ftrace_caller)
# ifdef CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST
/* optional micro optimization: return if stopped */
p1.l = _function_trace_stop;
p1.h = _function_trace_stop;
r3 = [p1];
cc = r3 == 0;
if ! cc jump _ftrace_stub (bp);
#endif
# endif
/* save first/second/third function arg and the return register */
[--sp] = r2;
[--sp] = r0;
[--sp] = r1;
[--sp] = rets;
/* function_trace_call(unsigned long ip, unsigned long parent_ip):
* ip: this point was called by ...
* parent_ip: ... this function
* the ip itself will need adjusting for the mcount call
*/
r0 = rets;
r1 = [sp + 16]; /* skip the 4 local regs on stack */
r0 += -MCOUNT_INSN_SIZE;
.globl _ftrace_call
_ftrace_call:
call _ftrace_stub
# ifdef CONFIG_FUNCTION_GRAPH_TRACER
.globl _ftrace_graph_call
_ftrace_graph_call:
nop; /* jump _ftrace_graph_caller; */
# endif
/* restore state and get out of dodge */
.Lfinish_trace:
rets = [sp++];
r1 = [sp++];
r0 = [sp++];
r2 = [sp++];
.globl _ftrace_stub
_ftrace_stub:
rts;
ENDPROC(_ftrace_caller)
#else
/* See documentation for _ftrace_caller */
ENTRY(__mcount)
# ifdef CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST
/* optional micro optimization: return if stopped */
p1.l = _function_trace_stop;
p1.h = _function_trace_stop;
r3 = [p1];
cc = r3 == 0;
if ! cc jump _ftrace_stub (bp);
# endif
/* save third function arg early so we can do testing below */
[--sp] = r2;
@ -44,7 +106,7 @@ ENTRY(__mcount)
cc = r2 == r3;
if ! cc jump .Ldo_trace;
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
# ifdef CONFIG_FUNCTION_GRAPH_TRACER
/* if the ftrace_graph_return function pointer is not set to
* the ftrace_stub entry, call prepare_ftrace_return().
*/
@ -64,7 +126,7 @@ ENTRY(__mcount)
r3 = [p0];
cc = r2 == r3;
if ! cc jump _ftrace_graph_caller;
#endif
# endif
r2 = [sp++];
rts;
@ -103,6 +165,8 @@ _ftrace_stub:
rts;
ENDPROC(__mcount)
#endif
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
/* The prepare_ftrace_return() function is similar to the trace function
* except it takes a pointer to the location of the frompc. This is so
@ -110,6 +174,7 @@ ENDPROC(__mcount)
* purposes.
*/
ENTRY(_ftrace_graph_caller)
# ifndef CONFIG_DYNAMIC_FTRACE
/* save first/second function arg and the return register */
[--sp] = r0;
[--sp] = r1;
@ -118,9 +183,13 @@ ENTRY(_ftrace_graph_caller)
/* prepare_ftrace_return(parent, self_addr, frame_pointer) */
r0 = sp; /* unsigned long *parent */
r1 = rets; /* unsigned long self_addr */
#ifdef CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST
# else
r0 = sp; /* unsigned long *parent */
r1 = [sp]; /* unsigned long self_addr */
# endif
# ifdef CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST
r2 = fp; /* unsigned long frame_pointer */
#endif
# endif
r0 += 16; /* skip the 4 local regs on stack */
r1 += -MCOUNT_INSN_SIZE;
call _prepare_ftrace_return;
@ -139,9 +208,9 @@ ENTRY(_return_to_handler)
[--sp] = r1;
/* get original return address */
#ifdef CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST
# ifdef CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST
r0 = fp; /* Blackfin is sane, so omit this */
#endif
# endif
call _ftrace_return_to_handler;
rets = r0;

86
arch/blackfin/kernel/ftrace.c
View file

@ -1,17 +1,101 @@
/*
* ftrace graph code
*
* Copyright (C) 2009 Analog Devices Inc.
* Copyright (C) 2009-2010 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#include <linux/ftrace.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/uaccess.h>
#include <asm/atomic.h>
#include <asm/cacheflush.h>
#ifdef CONFIG_DYNAMIC_FTRACE
static const unsigned char mnop[] = {
0x03, 0xc0, 0x00, 0x18, /* MNOP; */
0x03, 0xc0, 0x00, 0x18, /* MNOP; */
};
static void bfin_make_pcrel24(unsigned char *insn, unsigned long src,
unsigned long dst)
{
uint32_t pcrel = (dst - src) >> 1;
insn[0] = pcrel >> 16;
insn[1] = 0xe3;
insn[2] = pcrel;
insn[3] = pcrel >> 8;
}
#define bfin_make_pcrel24(insn, src, dst) bfin_make_pcrel24(insn, src, (unsigned long)(dst))
static int ftrace_modify_code(unsigned long ip, const unsigned char *code,
unsigned long len)
{
int ret = probe_kernel_write((void *)ip, (void *)code, len);
flush_icache_range(ip, ip + len);
return ret;
}
int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec,
unsigned long addr)
{
/* Turn the mcount call site into two MNOPs as those are 32bit insns */
return ftrace_modify_code(rec->ip, mnop, sizeof(mnop));
}
int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
{
/* Restore the mcount call site */
unsigned char call[8];
call[0] = 0x67; /* [--SP] = RETS; */
call[1] = 0x01;
bfin_make_pcrel24(&call[2], rec->ip + 2, addr);
call[6] = 0x27; /* RETS = [SP++]; */
call[7] = 0x01;
return ftrace_modify_code(rec->ip, call, sizeof(call));
}
int ftrace_update_ftrace_func(ftrace_func_t func)
{
unsigned char call[4];
unsigned long ip = (unsigned long)&ftrace_call;
bfin_make_pcrel24(call, ip, func);
return ftrace_modify_code(ip, call, sizeof(call));
}
int __init ftrace_dyn_arch_init(void *data)
{
/* return value is done indirectly via data */
*(unsigned long *)data = 0;
return 0;
}
#endif
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
# ifdef CONFIG_DYNAMIC_FTRACE
extern void ftrace_graph_call(void);
int ftrace_enable_ftrace_graph_caller(void)
{
unsigned long ip = (unsigned long)&ftrace_graph_call;
uint16_t jump_pcrel12 = ((unsigned long)&ftrace_graph_caller - ip) >> 1;
jump_pcrel12 |= 0x2000;
return ftrace_modify_code(ip, (void *)&jump_pcrel12, sizeof(jump_pcrel12));
}
int ftrace_disable_ftrace_graph_caller(void)
{
return ftrace_modify_code((unsigned long)&ftrace_graph_call, empty_zero_page, 2);
}
# endif
/*
* Hook the return address and push it in the stack of return addrs
* in current thread info.

7
arch/blackfin/kernel/setup.c
View file

@ -864,6 +864,13 @@ void __init setup_arch(char **cmdline_p)
bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
#endif
#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
bfin_write_PORTF_HYSTERISIS(HYST_PORTF_0_15);
bfin_write_PORTG_HYSTERISIS(HYST_PORTG_0_15);
bfin_write_PORTH_HYSTERISIS(HYST_PORTH_0_15);
bfin_write_MISCPORT_HYSTERISIS((bfin_read_MISCPORT_HYSTERISIS() &
~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
#endif
cclk = get_cclk();
sclk = get_sclk();

7
arch/blackfin/kernel/vmlinux.lds.S
View file

@ -48,15 +48,10 @@ SECTIONS
#if !L1_CODE_LENGTH
*(.l1.text)
#endif
. = ALIGN(16);
___start___ex_table = .;
*(__ex_table)
___stop___ex_table = .;
__etext = .;
}
EXCEPTION_TABLE(4)
NOTES
/* Just in case the first read only is a 32-bit access */

61
arch/blackfin/mach-bf518/Kconfig
View file

@ -62,6 +62,67 @@ config BF518_UART1_PORTG
PORT G
endchoice
comment "Hysteresis/Schmitt Trigger Control"
config BFIN_HYSTERESIS_CONTROL
bool "Enable Hysteresis Control"
help
The ADSP-BF51x allows to control input hysteresis for Port F,
Port G and Port H and other processor signal inputs.
The Schmitt trigger enables can be set only for pin groups.
Saying Y will overwrite the default reset or boot loader
initialization.
menu "PORT F"
depends on BFIN_HYSTERESIS_CONTROL
config GPIO_HYST_PORTF_0_7
bool "Enable Hysteresis on PORTF {0...7}"
config GPIO_HYST_PORTF_8_9
bool "Enable Hysteresis on PORTF {8, 9}"
config GPIO_HYST_PORTF_10
bool "Enable Hysteresis on PORTF 10"
config GPIO_HYST_PORTF_11
bool "Enable Hysteresis on PORTF 11"
config GPIO_HYST_PORTF_12_13
bool "Enable Hysteresis on PORTF {12, 13}"
config GPIO_HYST_PORTF_14_15
bool "Enable Hysteresis on PORTF {14, 15}"
endmenu
menu "PORT G"
depends on BFIN_HYSTERESIS_CONTROL
config GPIO_HYST_PORTG_0
bool "Enable Hysteresis on PORTG 0"
config GPIO_HYST_PORTG_1_4
bool "Enable Hysteresis on PORTG {1...4}"
config GPIO_HYST_PORTG_5_6
bool "Enable Hysteresis on PORTG {5, 6}"
config GPIO_HYST_PORTG_7_8
bool "Enable Hysteresis on PORTG {7, 8}"
config GPIO_HYST_PORTG_9
bool "Enable Hysteresis on PORTG 9"
config GPIO_HYST_PORTG_10
bool "Enable Hysteresis on PORTG 10"
config GPIO_HYST_PORTG_11_13
bool "Enable Hysteresis on PORTG {11...13}"
config GPIO_HYST_PORTG_14_15
bool "Enable Hysteresis on PORTG {14, 15}"
endmenu
menu "PORT H"
depends on BFIN_HYSTERESIS_CONTROL
config GPIO_HYST_PORTH_0_7
bool "Enable Hysteresis on PORTH {0...7}"
endmenu
menu "None-GPIO"
depends on BFIN_HYSTERESIS_CONTROL
config NONEGPIO_HYST_NMI_RST_BMODE
bool "Enable Hysteresis on {NMI, RESET, BMODE}"
config NONEGPIO_HYST_JTAG
bool "Enable Hysteresis on JTAG"
endmenu
comment "Interrupt Priority Assignment"
menu "Priority"

21
arch/blackfin/mach-bf518/include/mach/anomaly.h
View file

@ -5,13 +5,13 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2009 Analog Devices Inc.
* Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
* - Revision C, 06/12/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
* - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
*/
/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
@ -24,6 +24,8 @@
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
@ -52,6 +54,8 @@
#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
#define ANOMALY_05000431 (1)
/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
#define ANOMALY_05000434 (1)
/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
@ -74,14 +78,21 @@
#define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
/* PLL Latches Incorrect Settings During Reset */
#define ANOMALY_05000469 (1)
/* Incorrect Default MSEL Value in PLL_CTL */
#define ANOMALY_05000472 (1)
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
#define ANOMALY_05000473 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000119 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
@ -94,6 +105,7 @@
#define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000219 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
@ -143,5 +155,6 @@
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
#define ANOMALY_05000485 (0)
#endif

105
arch/blackfin/mach-bf518/include/mach/bf518.h
View file

@ -85,6 +85,111 @@
#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
/**************************** Hysteresis Settings ****************************/
#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
#ifdef CONFIG_GPIO_HYST_PORTF_0_7
#define HYST_PORTF_0_7 (1 << 0)
#else
#define HYST_PORTF_0_7 (0 << 0)
#endif
#ifdef CONFIG_GPIO_HYST_PORTF_8_9
#define HYST_PORTF_8_9 (1 << 2)
#else
#define HYST_PORTF_8_9 (0 << 2)
#endif
#ifdef CONFIG_GPIO_HYST_PORTF_10
#define HYST_PORTF_10 (1 << 4)
#else
#define HYST_PORTF_10 (0 << 4)
#endif
#ifdef CONFIG_GPIO_HYST_PORTF_11
#define HYST_PORTF_11 (1 << 6)
#else
#define HYST_PORTF_11 (0 << 6)
#endif
#ifdef CONFIG_GPIO_HYST_PORTF_12_13
#define HYST_PORTF_12_13 (1 << 8)
#else
#define HYST_PORTF_12_13 (0 << 8)
#endif
#ifdef CONFIG_GPIO_HYST_PORTF_14_15
#define HYST_PORTF_14_15 (1 << 10)
#else
#define HYST_PORTF_14_15 (0 << 10)
#endif
#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
#ifdef CONFIG_GPIO_HYST_PORTG_0
#define HYST_PORTG_0 (1 << 0)
#else
#define HYST_PORTG_0 (0 << 0)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_1_4
#define HYST_PORTG_1_4 (1 << 2)
#else
#define HYST_PORTG_1_4 (0 << 2)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_5_6
#define HYST_PORTG_5_6 (1 << 4)
#else
#define HYST_PORTG_5_6 (0 << 4)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_7_8
#define HYST_PORTG_7_8 (1 << 6)
#else
#define HYST_PORTG_7_8 (0 << 6)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_9
#define HYST_PORTG_9 (1 << 8)
#else
#define HYST_PORTG_9 (0 << 8)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_10
#define HYST_PORTG_10 (1 << 10)
#else
#define HYST_PORTG_10 (0 << 10)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_11_13
#define HYST_PORTG_11_13 (1 << 12)
#else
#define HYST_PORTG_11_13 (0 << 12)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_14_15
#define HYST_PORTG_14_15 (1 << 14)
#else
#define HYST_PORTG_14_15 (0 << 14)
#endif
#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
HYST_PORTG_11_13 | HYST_PORTG_14_15)
#ifdef CONFIG_GPIO_HYST_PORTH_0_7
#define HYST_PORTH_0_7 (1 << 0)
#else
#define HYST_PORTH_0_7 (0 << 0)
#endif
#define HYST_PORTH_0_15 (HYST_PORTH_0_7)
#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
#define HYST_NMI_RST_BMODE (1 << 2)
#else
#define HYST_NMI_RST_BMODE (0 << 2)
#endif
#ifdef CONFIG_NONEGPIO_HYST_JTAG
#define HYST_JTAG (1 << 4)
#else
#define HYST_JTAG (0 << 4)
#endif
#define HYST_NONEGPIO (HYST_NMI_RST_BMODE | HYST_JTAG)
#define HYST_NONEGPIO_MASK (0x3C)
#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
#ifdef CONFIG_BF518
#define CPU "BF518"
#define CPUID 0x27e8

135
arch/blackfin/mach-bf518/include/mach/defBF514.h
View file

@ -45,139 +45,4 @@
#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
/* ********************************************************** */
/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
/* and MULTI BIT READ MACROS */
/* ********************************************************** */
/* Bit masks for SDH_COMMAND */
#define CMD_IDX 0x3f /* Command Index */
#define CMD_RSP 0x40 /* Response */
#define CMD_L_RSP 0x80 /* Long Response */
#define CMD_INT_E 0x100 /* Command Interrupt */
#define CMD_PEND_E 0x200 /* Command Pending */
#define CMD_E 0x400 /* Command Enable */
/* Bit masks for SDH_PWR_CTL */
#define PWR_ON 0x3 /* Power On */
#if 0
#define TBD 0x3c /* TBD */
#endif
#define SD_CMD_OD 0x40 /* Open Drain Output */
#define ROD_CTL 0x80 /* Rod Control */
/* Bit masks for SDH_CLK_CTL */
#define CLKDIV 0xff /* MC_CLK Divisor */
#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
#define PWR_SV_E 0x200 /* Power Save Enable */
#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
/* Bit masks for SDH_RESP_CMD */
#define RESP_CMD 0x3f /* Response Command */
/* Bit masks for SDH_DATA_CTL */
#define DTX_E 0x1 /* Data Transfer Enable */
#define DTX_DIR 0x2 /* Data Transfer Direction */
#define DTX_MODE 0x4 /* Data Transfer Mode */
#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
/* Bit masks for SDH_STATUS */
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
#define CMD_TIME_OUT 0x4 /* CMD Time Out */
#define DAT_TIME_OUT 0x8 /* Data Time Out */
#define TX_UNDERRUN 0x10 /* Transmit Underrun */
#define RX_OVERRUN 0x20 /* Receive Overrun */
#define CMD_RESP_END 0x40 /* CMD Response End */
#define CMD_SENT 0x80 /* CMD Sent */
#define DAT_END 0x100 /* Data End */
#define START_BIT_ERR 0x200 /* Start Bit Error */
#define DAT_BLK_END 0x400 /* Data Block End */
#define CMD_ACT 0x800 /* CMD Active */
#define TX_ACT 0x1000 /* Transmit Active */
#define RX_ACT 0x2000 /* Receive Active */
#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
/* Bit masks for SDH_STATUS_CLR */
#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
#define DAT_END_STAT 0x100 /* Data End Status */
#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
/* Bit masks for SDH_MASK0 */
#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
#define DAT_END_MASK 0x100 /* Data End Mask */
#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
/* Bit masks for SDH_FIFO_CNT */
#define FIFO_COUNT 0x7fff /* FIFO Count */
/* Bit masks for SDH_E_STATUS */
#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
#define SD_CARD_DET 0x10 /* SD Card Detect */
/* Bit masks for SDH_E_MASK */
#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
#define SCD_MSK 0x40 /* Mask Card Detect */
/* Bit masks for SDH_CFG */
#define CLKS_EN 0x1 /* Clocks Enable */
#define SD4E 0x4 /* SDIO 4-Bit Enable */
#define MWE 0x8 /* Moving Window Enable */
#define SD_RST 0x10 /* SDMMC Reset */
#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
/* Bit masks for SDH_RD_WAIT_EN */
#define RWR 0x1 /* Read Wait Request */
#endif /* _DEF_BF514_H */

144
arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
View file

@ -458,22 +458,22 @@
/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
#define TWI0_REGBASE 0xFFC01400
#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
@ -1319,7 +1319,7 @@
#define TWI_ENA 0x0080 /* TWI Enable */
#define SCCB 0x0200 /* SCCB Compatibility Enable */
/* TWI_SLAVE_CTRL Masks */
/* TWI_SLAVE_CTL Masks */
#define SEN 0x0001 /* Slave Enable */
#define SADD_LEN 0x0002 /* Slave Address Length */
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
@ -1330,7 +1330,7 @@
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
#define GCALL 0x0002 /* General Call Indicator */
/* TWI_MASTER_CTRL Masks */
/* TWI_MASTER_CTL Masks */
#define MEN 0x0001 /* Master Mode Enable */
#define MADD_LEN 0x0002 /* Master Address Length */
#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
@ -1576,114 +1576,6 @@
#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
/* Bit masks for CNT_CONFIG */
#define CNTE 0x1 /* Counter Enable */
#define nCNTE 0x0
#define DEBE 0x2 /* Debounce Enable */
#define nDEBE 0x0
#define CDGINV 0x10 /* CDG Pin Polarity Invert */
#define nCDGINV 0x0
#define CUDINV 0x20 /* CUD Pin Polarity Invert */
#define nCUDINV 0x0
#define CZMINV 0x40 /* CZM Pin Polarity Invert */
#define nCZMINV 0x0
#define CNTMODE 0x700 /* Counter Operating Mode */
#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
#define nZMZC 0x0
#define BNDMODE 0x3000 /* Boundary register Mode */
#define INPDIS 0x8000 /* CUG and CDG Input Disable */
#define nINPDIS 0x0
/* Bit masks for CNT_IMASK */
#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
#define nICIE 0x0
#define UCIE 0x2 /* Up count Interrupt Enable */
#define nUCIE 0x0
#define DCIE 0x4 /* Down count Interrupt Enable */
#define nDCIE 0x0
#define MINCIE 0x8 /* Min Count Interrupt Enable */
#define nMINCIE 0x0
#define MAXCIE 0x10 /* Max Count Interrupt Enable */
#define nMAXCIE 0x0
#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
#define nCOV31IE 0x0
#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
#define nCOV15IE 0x0
#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
#define nCZEROIE 0x0
#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
#define nCZMIE 0x0
#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
#define nCZMEIE 0x0
#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
#define nCZMZIE 0x0
/* Bit masks for CNT_STATUS */
#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
#define nICII 0x0
#define UCII 0x2 /* Up count Interrupt Identifier */
#define nUCII 0x0
#define DCII 0x4 /* Down count Interrupt Identifier */
#define nDCII 0x0
#define MINCII 0x8 /* Min Count Interrupt Identifier */
#define nMINCII 0x0
#define MAXCII 0x10 /* Max Count Interrupt Identifier */
#define nMAXCII 0x0
#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
#define nCOV31II 0x0
#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
#define nCOV15II 0x0
#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
#define nCZEROII 0x0
#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
#define nCZMII 0x0
#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
#define nCZMEII 0x0
#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
#define nCZMZII 0x0
/* Bit masks for CNT_COMMAND */
#define W1LCNT 0xf /* Load Counter Register */
#define W1LMIN 0xf0 /* Load Min Register */
#define W1LMAX 0xf00 /* Load Max Register */
#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
#define nW1ZMONCE 0x0
/* Bit masks for CNT_DEBOUNCE */
#define DPRESCALE 0xf /* Load Counter Register */
/* CNT_COMMAND bit field options */
#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
/* CNT_CONFIG bit field options */
#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
#define BNDMODE_COMP 0x0000 /* boundary compare mode */
#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
/* Bit masks for SECURE_SYSSWT */
#define EMUDABL 0x1 /* Emulation Disable. */

83
arch/blackfin/mach-bf518/include/mach/gpio.h
View file

@ -7,48 +7,49 @@
#ifndef _MACH_GPIO_H_
#define _MACH_GPIO_H_
#define MAX_BLACKFIN_GPIOS 40
#define MAX_BLACKFIN_GPIOS 41
#define GPIO_PF0 0
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PG0 16
#define GPIO_PG1 17
#define GPIO_PG2 18
#define GPIO_PG3 19
#define GPIO_PG4 20
#define GPIO_PG5 21
#define GPIO_PG6 22
#define GPIO_PG7 23
#define GPIO_PG8 24
#define GPIO_PG9 25
#define GPIO_PG10 26
#define GPIO_PG11 27
#define GPIO_PG12 28
#define GPIO_PG13 29
#define GPIO_PG14 30
#define GPIO_PG15 31
#define GPIO_PH0 32
#define GPIO_PH1 33
#define GPIO_PH2 34
#define GPIO_PH3 35
#define GPIO_PH4 36
#define GPIO_PH5 37
#define GPIO_PH6 38
#define GPIO_PH7 39
#define GPIO_PF0 0
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PG0 16
#define GPIO_PG1 17
#define GPIO_PG2 18
#define GPIO_PG3 19
#define GPIO_PG4 20
#define GPIO_PG5 21
#define GPIO_PG6 22
#define GPIO_PG7 23
#define GPIO_PG8 24
#define GPIO_PG9 25
#define GPIO_PG10 26
#define GPIO_PG11 27
#define GPIO_PG12 28
#define GPIO_PG13 29
#define GPIO_PG14 30
#define GPIO_PG15 31
#define GPIO_PH0 32
#define GPIO_PH1 33
#define GPIO_PH2 34
#define GPIO_PH3 35
#define GPIO_PH4 36
#define GPIO_PH5 37
#define GPIO_PH6 38
#define GPIO_PH7 39
#define GPIO_PH8 40
#define PORT_F GPIO_PF0
#define PORT_G GPIO_PG0

7
arch/blackfin/mach-bf518/include/mach/portmux.h
View file

@ -7,7 +7,7 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
/* EMAC MII/RMII Port Mux */
#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
@ -95,7 +95,7 @@
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
@ -109,6 +109,7 @@
#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
/* SPORT Port Mux */
@ -195,6 +196,6 @@
#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG000000000) | P_FUNCT(1))
#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
#endif /* _MACH_PORTMUX_H_ */

66
arch/blackfin/mach-bf527/Kconfig
View file

@ -79,6 +79,72 @@ config BF527_NAND_D_PORTH
PORT H
endchoice
comment "Hysteresis/Schmitt Trigger Control"
config BFIN_HYSTERESIS_CONTROL
bool "Enable Hysteresis Control"
help
The ADSP-BF52x allows to control input hysteresis for Port F,
Port G and Port H and other processor signal inputs.
The Schmitt trigger enables can be set only for pin groups.
Saying Y will overwrite the default reset or boot loader
initialization.
menu "PORT F"
depends on BFIN_HYSTERESIS_CONTROL
config GPIO_HYST_PORTF_0_7
bool "Enable Hysteresis on PORTF {0...7}"
config GPIO_HYST_PORTF_8_9
bool "Enable Hysteresis on PORTF {8, 9}"
config GPIO_HYST_PORTF_10
bool "Enable Hysteresis on PORTF 10"
config GPIO_HYST_PORTF_11
bool "Enable Hysteresis on PORTF 11"
config GPIO_HYST_PORTF_12_13
bool "Enable Hysteresis on PORTF {12, 13}"
config GPIO_HYST_PORTF_14_15
bool "Enable Hysteresis on PORTF {14, 15}"
endmenu
menu "PORT G"
depends on BFIN_HYSTERESIS_CONTROL
config GPIO_HYST_PORTG_0
bool "Enable Hysteresis on PORTG 0"
config GPIO_HYST_PORTG_1_4
bool "Enable Hysteresis on PORTG {1...4}"
config GPIO_HYST_PORTG_5_6
bool "Enable Hysteresis on PORTG {5, 6}"
config GPIO_HYST_PORTG_7_8
bool "Enable Hysteresis on PORTG {7, 8}"
config GPIO_HYST_PORTG_9
bool "Enable Hysteresis on PORTG 9"
config GPIO_HYST_PORTG_10
bool "Enable Hysteresis on PORTG 10"
config GPIO_HYST_PORTG_11_13
bool "Enable Hysteresis on PORTG {11...13}"
config GPIO_HYST_PORTG_14_15
bool "Enable Hysteresis on PORTG {14, 15}"
endmenu
menu "PORT H"
depends on BFIN_HYSTERESIS_CONTROL
config GPIO_HYST_PORTH_0_7
bool "Enable Hysteresis on PORTH {0...7}"
config GPIO_HYST_PORTH_8
bool "Enable Hysteresis on PORTH 8"
config GPIO_HYST_PORTH_9_15
bool "Enable Hysteresis on PORTH {9...15}"
endmenu
menu "None-GPIO"
depends on BFIN_HYSTERESIS_CONTROL
config NONEGPIO_HYST_TMR0_FS1_PPICLK
bool "Enable Hysteresis on {TMR0, PPI_FS1, PPI_CLK}"
config NONEGPIO_HYST_NMI_RST_BMODE
bool "Enable Hysteresis on {NMI, RESET, BMODE}"
config NONEGPIO_HYST_JTAG
bool "Enable Hysteresis on JTAG"
endmenu
comment "Interrupt Priority Assignment"
menu "Priority"

22
arch/blackfin/mach-bf527/include/mach/anomaly.h
View file

@ -5,13 +5,13 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2009 Analog Devices Inc.
* Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
* - Revision D, 08/14/2009; ADSP-BF526 Blackfin Processor Anomaly List
* - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
* - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List
*/
@ -41,7 +41,7 @@
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
@ -168,6 +168,8 @@
#define ANOMALY_05000431 (1)
/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
#define ANOMALY_05000434 (1)
/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
/* Preboot Cannot be Used to Alter the PLL_DIV Register */
@ -204,10 +206,22 @@
#define ANOMALY_05000467 (1)
/* PLL Latches Incorrect Settings During Reset */
#define ANOMALY_05000469 (1)
/* Incorrect Default MSEL Value in PLL_CTL */
#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
#define ANOMALY_05000483 (1)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
@ -223,6 +237,7 @@
#define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000219 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
@ -259,6 +274,5 @@
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
#endif

120
arch/blackfin/mach-bf527/include/mach/bf527.h
View file

@ -85,6 +85,126 @@
#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
/**************************** Hysteresis Settings ****************************/
#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
#ifdef CONFIG_GPIO_HYST_PORTF_0_7
#define HYST_PORTF_0_7 (1 << 0)
#else
#define HYST_PORTF_0_7 (0 << 0)
#endif
#ifdef CONFIG_GPIO_HYST_PORTF_8_9
#define HYST_PORTF_8_9 (1 << 2)
#else
#define HYST_PORTF_8_9 (0 << 2)
#endif
#ifdef CONFIG_GPIO_HYST_PORTF_10
#define HYST_PORTF_10 (1 << 4)
#else
#define HYST_PORTF_10 (0 << 4)
#endif
#ifdef CONFIG_GPIO_HYST_PORTF_11
#define HYST_PORTF_11 (1 << 6)
#else
#define HYST_PORTF_11 (0 << 6)
#endif
#ifdef CONFIG_GPIO_HYST_PORTF_12_13
#define HYST_PORTF_12_13 (1 << 8)
#else
#define HYST_PORTF_12_13 (0 << 8)
#endif
#ifdef CONFIG_GPIO_HYST_PORTF_14_15
#define HYST_PORTF_14_15 (1 << 10)
#else
#define HYST_PORTF_14_15 (0 << 10)
#endif
#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
#ifdef CONFIG_GPIO_HYST_PORTG_0
#define HYST_PORTG_0 (1 << 0)
#else
#define HYST_PORTG_0 (0 << 0)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_1_4
#define HYST_PORTG_1_4 (1 << 2)
#else
#define HYST_PORTG_1_4 (0 << 2)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_5_6
#define HYST_PORTG_5_6 (1 << 4)
#else
#define HYST_PORTG_5_6 (0 << 4)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_7_8
#define HYST_PORTG_7_8 (1 << 6)
#else
#define HYST_PORTG_7_8 (0 << 6)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_9
#define HYST_PORTG_9 (1 << 8)
#else
#define HYST_PORTG_9 (0 << 8)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_10
#define HYST_PORTG_10 (1 << 10)
#else
#define HYST_PORTG_10 (0 << 10)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_11_13
#define HYST_PORTG_11_13 (1 << 12)
#else
#define HYST_PORTG_11_13 (0 << 12)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_14_15
#define HYST_PORTG_14_15 (1 << 14)
#else
#define HYST_PORTG_14_15 (0 << 14)
#endif
#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
HYST_PORTG_11_13 | HYST_PORTG_14_15)
#ifdef CONFIG_GPIO_HYST_PORTH_0_7
#define HYST_PORTH_0_7 (1 << 0)
#else
#define HYST_PORTH_0_7 (0 << 0)
#endif
#ifdef CONFIG_GPIO_HYST_PORTH_8
#define HYST_PORTH_8 (1 << 2)
#else
#define HYST_PORTH_8 (0 << 2)
#endif
#ifdef CONFIG_GPIO_HYST_PORTH_9_15
#define HYST_PORTH_9_15 (1 << 4)
#else
#define HYST_PORTH_9_15 (0 << 4)
#endif
#define HYST_PORTH_0_15 (HYST_PORTH_0_7 | HYST_PORTH_8 | HYST_PORTH_9_15)
#ifdef CONFIG_NONEGPIO_HYST_TMR0_FS1_PPICLK
#define HYST_TMR0_FS1_PPICLK (1 << 0)
#else
#define HYST_TMR0_FS1_PPICLK (0 << 0)
#endif
#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
#define HYST_NMI_RST_BMODE (1 << 2)
#else
#define HYST_NMI_RST_BMODE (0 << 2)
#endif
#ifdef CONFIG_NONEGPIO_HYST_JTAG
#define HYST_JTAG (1 << 4)
#else
#define HYST_JTAG (0 << 4)
#endif
#define HYST_NONEGPIO (HYST_TMR0_FS1_PPICLK | HYST_NMI_RST_BMODE | HYST_JTAG)
#define HYST_NONEGPIO_MASK (0x3F)
#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
#ifdef CONFIG_BF527
#define CPU "BF527"
#define CPUID 0x27e0

225
arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
View file

@ -458,22 +458,22 @@
/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
#define TWI0_REGBASE 0xFFC01400
#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
@ -1328,7 +1328,7 @@
#define TWI_ENA 0x0080 /* TWI Enable */
#define SCCB 0x0200 /* SCCB Compatibility Enable */
/* TWI_SLAVE_CTRL Masks */
/* TWI_SLAVE_CTL Masks */
#define SEN 0x0001 /* Slave Enable */
#define SADD_LEN 0x0002 /* Slave Address Length */
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
@ -1339,7 +1339,7 @@
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
#define GCALL 0x0002 /* General Call Indicator */
/* TWI_MASTER_CTRL Masks */
/* TWI_MASTER_CTL Masks */
#define MEN 0x0001 /* Master Mode Enable */
#define MADD_LEN 0x0002 /* Master Address Length */
#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
@ -1589,114 +1589,6 @@
#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */
/* Bit masks for CNT_CONFIG */
#define CNTE 0x1 /* Counter Enable */
#define nCNTE 0x0
#define DEBE 0x2 /* Debounce Enable */
#define nDEBE 0x0
#define CDGINV 0x10 /* CDG Pin Polarity Invert */
#define nCDGINV 0x0
#define CUDINV 0x20 /* CUD Pin Polarity Invert */
#define nCUDINV 0x0
#define CZMINV 0x40 /* CZM Pin Polarity Invert */
#define nCZMINV 0x0
#define CNTMODE 0x700 /* Counter Operating Mode */
#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
#define nZMZC 0x0
#define BNDMODE 0x3000 /* Boundary register Mode */
#define INPDIS 0x8000 /* CUG and CDG Input Disable */
#define nINPDIS 0x0
/* Bit masks for CNT_IMASK */
#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
#define nICIE 0x0
#define UCIE 0x2 /* Up count Interrupt Enable */
#define nUCIE 0x0
#define DCIE 0x4 /* Down count Interrupt Enable */
#define nDCIE 0x0
#define MINCIE 0x8 /* Min Count Interrupt Enable */
#define nMINCIE 0x0
#define MAXCIE 0x10 /* Max Count Interrupt Enable */
#define nMAXCIE 0x0
#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
#define nCOV31IE 0x0
#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
#define nCOV15IE 0x0
#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
#define nCZEROIE 0x0
#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
#define nCZMIE 0x0
#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
#define nCZMEIE 0x0
#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
#define nCZMZIE 0x0
/* Bit masks for CNT_STATUS */
#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
#define nICII 0x0
#define UCII 0x2 /* Up count Interrupt Identifier */
#define nUCII 0x0
#define DCII 0x4 /* Down count Interrupt Identifier */
#define nDCII 0x0
#define MINCII 0x8 /* Min Count Interrupt Identifier */
#define nMINCII 0x0
#define MAXCII 0x10 /* Max Count Interrupt Identifier */
#define nMAXCII 0x0
#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
#define nCOV31II 0x0
#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
#define nCOV15II 0x0
#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
#define nCZEROII 0x0
#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
#define nCZMII 0x0
#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
#define nCZMEII 0x0
#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
#define nCZMZII 0x0
/* Bit masks for CNT_COMMAND */
#define W1LCNT 0xf /* Load Counter Register */
#define W1LMIN 0xf0 /* Load Min Register */
#define W1LMAX 0xf00 /* Load Max Register */
#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
#define nW1ZMONCE 0x0
/* Bit masks for CNT_DEBOUNCE */
#define DPRESCALE 0xf /* Load Counter Register */
/* CNT_COMMAND bit field options */
#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
/* CNT_CONFIG bit field options */
#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
#define BNDMODE_COMP 0x0000 /* boundary compare mode */
#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
/* Bit masks for SECURE_SYSSWT */
#define EMUDABL 0x1 /* Emulation Disable. */
@ -1738,85 +1630,4 @@
#define nAFEXIT 0x0
#define SECSTAT 0xe0 /* Secure Status */
/* Bit masks for NFC_CTL */
#define WR_DLY 0xf /* Write Strobe Delay */
#define RD_DLY 0xf0 /* Read Strobe Delay */
#define NWIDTH 0x100 /* NAND Data Width */
#define nNWIDTH 0x0
#define PG_SIZE 0x200 /* Page Size */
#define nPG_SIZE 0x0
/* Bit masks for NFC_STAT */
#define NBUSY 0x1 /* Not Busy */
#define nNBUSY 0x0
#define WB_FULL 0x2 /* Write Buffer Full */
#define nWB_FULL 0x0
#define PG_WR_STAT 0x4 /* Page Write Pending */
#define nPG_WR_STAT 0x0
#define PG_RD_STAT 0x8 /* Page Read Pending */
#define nPG_RD_STAT 0x0
#define WB_EMPTY 0x10 /* Write Buffer Empty */
#define nWB_EMPTY 0x0
/* Bit masks for NFC_IRQSTAT */
#define NBUSYIRQ 0x1 /* Not Busy IRQ */
#define nNBUSYIRQ 0x0
#define WB_OVF 0x2 /* Write Buffer Overflow */
#define nWB_OVF 0x0
#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
#define nWB_EDGE 0x0
#define RD_RDY 0x8 /* Read Data Ready */
#define nRD_RDY 0x0
#define WR_DONE 0x10 /* Page Write Done */
#define nWR_DONE 0x0
/* Bit masks for NFC_IRQMASK */
#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
#define nMASK_BUSYIRQ 0x0
#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
#define nMASK_WBOVF 0x0
#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
#define nMASK_WBEMPTY 0x0
#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
#define nMASK_RDRDY 0x0
#define MASK_WRDONE 0x10 /* Mask Write Done */
#define nMASK_WRDONE 0x0
/* Bit masks for NFC_RST */
#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
#define nECC_RST 0x0
/* Bit masks for NFC_PGCTL */
#define PG_RD_START 0x1 /* Page Read Start */
#define nPG_RD_START 0x0
#define PG_WR_START 0x2 /* Page Write Start */
#define nPG_WR_START 0x0
/* Bit masks for NFC_ECC0 */
#define ECC0 0x7ff /* Parity Calculation Result0 */
/* Bit masks for NFC_ECC1 */
#define ECC1 0x7ff /* Parity Calculation Result1 */
/* Bit masks for NFC_ECC2 */
#define ECC2 0x7ff /* Parity Calculation Result2 */
/* Bit masks for NFC_ECC3 */
#define ECC3 0x7ff /* Parity Calculation Result3 */
/* Bit masks for NFC_COUNT */
#define ECCCNT 0x3ff /* Transfer Count */
#endif /* _DEF_BF52X_H */

96
arch/blackfin/mach-bf527/include/mach/gpio.h
View file

@ -9,54 +9,54 @@
#define MAX_BLACKFIN_GPIOS 48
#define GPIO_PF0 0
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PG0 16
#define GPIO_PG1 17
#define GPIO_PG2 18
#define GPIO_PG3 19
#define GPIO_PG4 20
#define GPIO_PG5 21
#define GPIO_PG6 22
#define GPIO_PG7 23
#define GPIO_PG8 24
#define GPIO_PG9 25
#define GPIO_PG10 26
#define GPIO_PG11 27
#define GPIO_PG12 28
#define GPIO_PG13 29
#define GPIO_PG14 30
#define GPIO_PG15 31
#define GPIO_PH0 32
#define GPIO_PH1 33
#define GPIO_PH2 34
#define GPIO_PH3 35
#define GPIO_PH4 36
#define GPIO_PH5 37
#define GPIO_PH6 38
#define GPIO_PH7 39
#define GPIO_PH8 40
#define GPIO_PH9 41
#define GPIO_PH10 42
#define GPIO_PH11 43
#define GPIO_PH12 44
#define GPIO_PH13 45
#define GPIO_PH14 46
#define GPIO_PH15 47
#define GPIO_PF0 0
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PG0 16
#define GPIO_PG1 17
#define GPIO_PG2 18
#define GPIO_PG3 19
#define GPIO_PG4 20
#define GPIO_PG5 21
#define GPIO_PG6 22
#define GPIO_PG7 23
#define GPIO_PG8 24
#define GPIO_PG9 25
#define GPIO_PG10 26
#define GPIO_PG11 27
#define GPIO_PG12 28
#define GPIO_PG13 29
#define GPIO_PG14 30
#define GPIO_PG15 31
#define GPIO_PH0 32
#define GPIO_PH1 33
#define GPIO_PH2 34
#define GPIO_PH3 35
#define GPIO_PH4 36
#define GPIO_PH5 37
#define GPIO_PH6 38
#define GPIO_PH7 39
#define GPIO_PH8 40
#define GPIO_PH9 41
#define GPIO_PH10 42
#define GPIO_PH11 43
#define GPIO_PH12 44
#define GPIO_PH13 45
#define GPIO_PH14 46
#define GPIO_PH15 47
#define PORT_F GPIO_PF0
#define PORT_G GPIO_PG0

3
arch/blackfin/mach-bf527/include/mach/portmux.h
View file

@ -7,7 +7,7 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
@ -79,6 +79,7 @@
#define P_HWAIT (P_DONTCARE)
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))

10
arch/blackfin/mach-bf533/include/mach/anomaly.h
View file

@ -5,7 +5,7 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2009 Analog Devices Inc.
* Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
@ -208,8 +208,14 @@
#define ANOMALY_05000461 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
/* These anomalies have been "phased" out of analog.com anomaly sheets and are
* here to show running on older silicon just isn't feasible.
@ -358,6 +364,6 @@
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
#define ANOMALY_05000485 (0)
#endif

32
arch/blackfin/mach-bf533/include/mach/gpio.h
View file

@ -9,22 +9,22 @@
#define MAX_BLACKFIN_GPIOS 16
#define GPIO_PF0 0
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PF0 0
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define PORT_F GPIO_PF0

3
arch/blackfin/mach-bf533/include/mach/portmux.h
View file

@ -7,7 +7,7 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
#define P_PPI0_CLK (P_DONTCARE)
#define P_PPI0_FS1 (P_DONTCARE)
@ -60,6 +60,7 @@
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
#define P_TMR2 (P_DONTCARE)

11
arch/blackfin/mach-bf537/include/mach/anomaly.h
View file

@ -5,7 +5,7 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2009 Analog Devices Inc.
* Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
@ -162,8 +162,14 @@
#define ANOMALY_05000461 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
@ -179,6 +185,7 @@
#define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000219 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
@ -211,6 +218,6 @@
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
#define ANOMALY_05000485 (0)
#endif

36
arch/blackfin/mach-bf537/include/mach/defBF534.h
View file

@ -434,22 +434,22 @@
/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
#define TWI0_REGBASE 0xFFC01400
#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
#define TWI0_CONTROL 0xFFC01404 /* TWI Control Register */
#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
#define TWI0_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
#define TWI0_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
@ -1642,7 +1642,7 @@
#define TWI_ENA 0x0080 /* TWI Enable */
#define SCCB 0x0200 /* SCCB Compatibility Enable */
/* TWI_SLAVE_CTRL Masks */
/* TWI_SLAVE_CTL Masks */
#define SEN 0x0001 /* Slave Enable */
#define SADD_LEN 0x0002 /* Slave Address Length */
#define STDVAL 0x0004 /* Slave Transmit Data Valid */
@ -1653,7 +1653,7 @@
#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
#define GCALL 0x0002 /* General Call Indicator */
/* TWI_MASTER_CTRL Masks */
/* TWI_MASTER_CTL Masks */
#define MEN 0x0001 /* Master Mode Enable */
#define MADD_LEN 0x0002 /* Master Address Length */
#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */

96
arch/blackfin/mach-bf537/include/mach/gpio.h
View file

@ -9,54 +9,54 @@
#define MAX_BLACKFIN_GPIOS 48
#define GPIO_PF0 0
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PG0 16
#define GPIO_PG1 17
#define GPIO_PG2 18
#define GPIO_PG3 19
#define GPIO_PG4 20
#define GPIO_PG5 21
#define GPIO_PG6 22
#define GPIO_PG7 23
#define GPIO_PG8 24
#define GPIO_PG9 25
#define GPIO_PG10 26
#define GPIO_PG11 27
#define GPIO_PG12 28
#define GPIO_PG13 29
#define GPIO_PG14 30
#define GPIO_PG15 31
#define GPIO_PH0 32
#define GPIO_PH1 33
#define GPIO_PH2 34
#define GPIO_PH3 35
#define GPIO_PH4 36
#define GPIO_PH5 37
#define GPIO_PH6 38
#define GPIO_PH7 39
#define GPIO_PH8 40
#define GPIO_PH9 41
#define GPIO_PH10 42
#define GPIO_PH11 43
#define GPIO_PH12 44
#define GPIO_PH13 45
#define GPIO_PH14 46
#define GPIO_PH15 47
#define GPIO_PF0 0
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PG0 16
#define GPIO_PG1 17
#define GPIO_PG2 18
#define GPIO_PG3 19
#define GPIO_PG4 20
#define GPIO_PG5 21
#define GPIO_PG6 22
#define GPIO_PG7 23
#define GPIO_PG8 24
#define GPIO_PG9 25
#define GPIO_PG10 26
#define GPIO_PG11 27
#define GPIO_PG12 28
#define GPIO_PG13 29
#define GPIO_PG14 30
#define GPIO_PG15 31
#define GPIO_PH0 32
#define GPIO_PH1 33
#define GPIO_PH2 34
#define GPIO_PH3 35
#define GPIO_PH4 36
#define GPIO_PH5 37
#define GPIO_PH6 38
#define GPIO_PH7 39
#define GPIO_PH8 40
#define GPIO_PH9 41
#define GPIO_PH10 42
#define GPIO_PH11 43
#define GPIO_PH12 44
#define GPIO_PH13 45
#define GPIO_PH14 46
#define GPIO_PH15 47
#define PORT_F GPIO_PF0
#define PORT_G GPIO_PG0

7
arch/blackfin/mach-bf537/include/mach/portmux.h
View file

@ -7,7 +7,7 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
#define MAX_RESOURCES (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE) /* We additionally handle PORTJ */
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
@ -37,6 +37,7 @@
#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
@ -135,7 +136,6 @@
P_MDC, \
P_MDIO, 0}
#define P_RMII0 {\
P_MII0_ETxD0, \
P_MII0_ETxD1, \
@ -148,4 +148,5 @@
P_RMII0_CRS_DV, \
P_MDC, \
P_MDIO, 0}
#endif /* _MACH_PORTMUX_H_ */
#endif /* _MACH_PORTMUX_H_ */

16
arch/blackfin/mach-bf538/include/mach/anomaly.h
View file

@ -5,14 +5,14 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2009 Analog Devices Inc.
* Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
* - Revision G, 09/18/2008; ADSP-BF538/BF538F Blackfin Processor Anomaly List
* - Revision L, 09/18/2008; ADSP-BF539/BF539F Blackfin Processor Anomaly List
* - Revision H, 07/10/2009; ADSP-BF538/BF538F Blackfin Processor Anomaly List
* - Revision M, 07/10/2009; ADSP-BF539/BF539F Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@ -132,10 +132,18 @@
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
@ -185,6 +193,6 @@
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
#define ANOMALY_05000485 (0)
#endif

64
arch/blackfin/mach-bf538/include/mach/cdefBF538.h
View file

@ -1293,70 +1293,6 @@
#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
#define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
#define bfin_read_TWI0_MASTER_CTL() bfin_read16(TWI0_MASTER_CTL)
#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
#define bfin_read_TWI0_FIFO_CTL() bfin_read16(TWI0_FIFO_CTL)
#define bfin_write_TWI0_FIFO_CTL(val) bfin_write16(TWI0_FIFO_CTL, val)
#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
#define bfin_read_TWI1_MASTER_CTL() bfin_read16(TWI1_MASTER_CTL)
#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
#define bfin_read_TWI1_FIFO_CTL() bfin_read16(TWI1_FIFO_CTL)
#define bfin_write_TWI1_FIFO_CTL(val) bfin_write16(TWI1_FIFO_CTL, val)
#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val)
#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)

14
arch/blackfin/mach-bf538/include/mach/defBF539.h
View file

@ -442,15 +442,15 @@
/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */
#define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */
#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
#define TWI0_MASTER_CTRL 0xFFC01414 /* Master Mode Control Register */
#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */
#define TWI0_FIFO_CTRL 0xFFC01428 /* FIFO Control Register */
#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
@ -761,15 +761,15 @@
/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */
#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
#define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */
#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */
#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
#define TWI1_MASTER_CTRL 0xFFC02214 /* Master Mode Control Register */
#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */
#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
#define TWI1_FIFO_CTRL 0xFFC02228 /* FIFO Control Register */
#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */
#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */
#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */
@ -2401,7 +2401,7 @@
#define XMTSERV 0x0040 /* Transmit FIFO Service */
#define RCVSERV 0x0080 /* Receive FIFO Service */
/* TWIx_FIFO_CTRL Masks */
/* TWIx_FIFO_CTL Masks */
#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */

108
arch/blackfin/mach-bf538/include/mach/gpio.h
View file

@ -10,60 +10,60 @@
#define MAX_BLACKFIN_GPIOS 16
#define BFIN_SPECIAL_GPIO_BANKS 3
#define GPIO_PF0 0 /* PF */
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PC0 16 /* PC */
#define GPIO_PC1 17
#define GPIO_PC4 20
#define GPIO_PC5 21
#define GPIO_PC6 22
#define GPIO_PC7 23
#define GPIO_PC8 24
#define GPIO_PC9 25
#define GPIO_PD0 32 /* PD */
#define GPIO_PD1 33
#define GPIO_PD2 34
#define GPIO_PD3 35
#define GPIO_PD4 36
#define GPIO_PD5 37
#define GPIO_PD6 38
#define GPIO_PD7 39
#define GPIO_PD8 40
#define GPIO_PD9 41
#define GPIO_PD10 42
#define GPIO_PD11 43
#define GPIO_PD12 44
#define GPIO_PD13 45
#define GPIO_PE0 48 /* PE */
#define GPIO_PE1 49
#define GPIO_PE2 50
#define GPIO_PE3 51
#define GPIO_PE4 52
#define GPIO_PE5 53
#define GPIO_PE6 54
#define GPIO_PE7 55
#define GPIO_PE8 56
#define GPIO_PE9 57
#define GPIO_PE10 58
#define GPIO_PE11 59
#define GPIO_PE12 60
#define GPIO_PE13 61
#define GPIO_PE14 62
#define GPIO_PE15 63
#define GPIO_PF0 0 /* PF */
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PC0 16 /* PC */
#define GPIO_PC1 17
#define GPIO_PC4 20
#define GPIO_PC5 21
#define GPIO_PC6 22
#define GPIO_PC7 23
#define GPIO_PC8 24
#define GPIO_PC9 25
#define GPIO_PD0 32 /* PD */
#define GPIO_PD1 33
#define GPIO_PD2 34
#define GPIO_PD3 35
#define GPIO_PD4 36
#define GPIO_PD5 37
#define GPIO_PD6 38
#define GPIO_PD7 39
#define GPIO_PD8 40
#define GPIO_PD9 41
#define GPIO_PD10 42
#define GPIO_PD11 43
#define GPIO_PD12 44
#define GPIO_PD13 45
#define GPIO_PE0 48 /* PE */
#define GPIO_PE1 49
#define GPIO_PE2 50
#define GPIO_PE3 51
#define GPIO_PE4 52
#define GPIO_PE5 53
#define GPIO_PE6 54
#define GPIO_PE7 55
#define GPIO_PE8 56
#define GPIO_PE9 57
#define GPIO_PE10 58
#define GPIO_PE11 59
#define GPIO_PE12 60
#define GPIO_PE13 61
#define GPIO_PE14 62
#define GPIO_PE15 63
#define PORT_F GPIO_PF0
#define PORT_C GPIO_PC0

1
arch/blackfin/mach-bf538/include/mach/portmux.h
View file

@ -108,6 +108,7 @@
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
#endif /* _MACH_PORTMUX_H_ */

16
arch/blackfin/mach-bf548/include/mach/anomaly.h
View file

@ -5,7 +5,7 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2009 Analog Devices Inc.
* Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
@ -28,7 +28,7 @@
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
#define ANOMALY_05000220 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
@ -210,10 +210,16 @@
#define ANOMALY_05000473 (1)
/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
#define ANOMALY_05000474 (1)
/* Core Hang With L2/L3 Configured in Writeback Cache Mode */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
#define ANOMALY_05000483 (1)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
@ -229,6 +235,7 @@
#define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000219 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
@ -263,5 +270,6 @@
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
#define ANOMALY_05000475 (0)
#endif

16
arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
View file

@ -301,10 +301,10 @@
/* DMAC0 Registers */
#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER, val)
#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT, val)
/* DMA Channel 0 Registers */
@ -1155,10 +1155,10 @@
/* DMAC1 Registers */
#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER, val)
#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT, val)
/* DMA Channel 12 Registers */

130
arch/blackfin/mach-bf548/include/mach/defBF542.h
View file

@ -366,136 +366,6 @@
#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
/* Bit masks for SDH_COMMAND */
#define CMD_IDX 0x3f /* Command Index */
#define CMD_RSP 0x40 /* Response */
#define CMD_L_RSP 0x80 /* Long Response */
#define CMD_INT_E 0x100 /* Command Interrupt */
#define CMD_PEND_E 0x200 /* Command Pending */
#define CMD_E 0x400 /* Command Enable */
/* Bit masks for SDH_PWR_CTL */
#define PWR_ON 0x3 /* Power On */
#if 0
#define TBD 0x3c /* TBD */
#endif
#define SD_CMD_OD 0x40 /* Open Drain Output */
#define ROD_CTL 0x80 /* Rod Control */
/* Bit masks for SDH_CLK_CTL */
#define CLKDIV 0xff /* MC_CLK Divisor */
#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
#define PWR_SV_E 0x200 /* Power Save Enable */
#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
/* Bit masks for SDH_RESP_CMD */
#define RESP_CMD 0x3f /* Response Command */
/* Bit masks for SDH_DATA_CTL */
#define DTX_E 0x1 /* Data Transfer Enable */
#define DTX_DIR 0x2 /* Data Transfer Direction */
#define DTX_MODE 0x4 /* Data Transfer Mode */
#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
/* Bit masks for SDH_STATUS */
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
#define CMD_TIME_OUT 0x4 /* CMD Time Out */
#define DAT_TIME_OUT 0x8 /* Data Time Out */
#define TX_UNDERRUN 0x10 /* Transmit Underrun */
#define RX_OVERRUN 0x20 /* Receive Overrun */
#define CMD_RESP_END 0x40 /* CMD Response End */
#define CMD_SENT 0x80 /* CMD Sent */
#define DAT_END 0x100 /* Data End */
#define START_BIT_ERR 0x200 /* Start Bit Error */
#define DAT_BLK_END 0x400 /* Data Block End */
#define CMD_ACT 0x800 /* CMD Active */
#define TX_ACT 0x1000 /* Transmit Active */
#define RX_ACT 0x2000 /* Receive Active */
#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
/* Bit masks for SDH_STATUS_CLR */
#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
#define DAT_END_STAT 0x100 /* Data End Status */
#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
/* Bit masks for SDH_MASK0 */
#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
#define DAT_END_MASK 0x100 /* Data End Mask */
#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
/* Bit masks for SDH_FIFO_CNT */
#define FIFO_COUNT 0x7fff /* FIFO Count */
/* Bit masks for SDH_E_STATUS */
#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
#define SD_CARD_DET 0x10 /* SD Card Detect */
/* Bit masks for SDH_E_MASK */
#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
#define SCD_MSK 0x40 /* Mask Card Detect */
/* Bit masks for SDH_CFG */
#define CLKS_EN 0x1 /* Clocks Enable */
#define SD4E 0x4 /* SDIO 4-Bit Enable */
#define MWE 0x8 /* Moving Window Enable */
#define SD_RST 0x10 /* SDMMC Reset */
#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
/* Bit masks for SDH_RD_WAIT_EN */
#define RWR 0x1 /* Read Wait Request */
/* Bit masks for ATAPI_CONTROL */
#define PIO_START 0x1 /* Start PIO/Reg Op */

6
arch/blackfin/mach-bf548/include/mach/defBF544.h
View file

@ -60,15 +60,15 @@
#define TWI1_REGBASE 0xffc02200
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */

136
arch/blackfin/mach-bf548/include/mach/defBF547.h
View file

@ -99,15 +99,15 @@
#define TWI1_REGBASE 0xffc02200
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
@ -646,136 +646,6 @@
#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
/* Bit masks for SDH_COMMAND */
#define CMD_IDX 0x3f /* Command Index */
#define CMD_RSP 0x40 /* Response */
#define CMD_L_RSP 0x80 /* Long Response */
#define CMD_INT_E 0x100 /* Command Interrupt */
#define CMD_PEND_E 0x200 /* Command Pending */
#define CMD_E 0x400 /* Command Enable */
/* Bit masks for SDH_PWR_CTL */
#define PWR_ON 0x3 /* Power On */
#if 0
#define TBD 0x3c /* TBD */
#endif
#define SD_CMD_OD 0x40 /* Open Drain Output */
#define ROD_CTL 0x80 /* Rod Control */
/* Bit masks for SDH_CLK_CTL */
#define CLKDIV 0xff /* MC_CLK Divisor */
#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
#define PWR_SV_E 0x200 /* Power Save Enable */
#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
/* Bit masks for SDH_RESP_CMD */
#define RESP_CMD 0x3f /* Response Command */
/* Bit masks for SDH_DATA_CTL */
#define DTX_E 0x1 /* Data Transfer Enable */
#define DTX_DIR 0x2 /* Data Transfer Direction */
#define DTX_MODE 0x4 /* Data Transfer Mode */
#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
/* Bit masks for SDH_STATUS */
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
#define CMD_TIME_OUT 0x4 /* CMD Time Out */
#define DAT_TIME_OUT 0x8 /* Data Time Out */
#define TX_UNDERRUN 0x10 /* Transmit Underrun */
#define RX_OVERRUN 0x20 /* Receive Overrun */
#define CMD_RESP_END 0x40 /* CMD Response End */
#define CMD_SENT 0x80 /* CMD Sent */
#define DAT_END 0x100 /* Data End */
#define START_BIT_ERR 0x200 /* Start Bit Error */
#define DAT_BLK_END 0x400 /* Data Block End */
#define CMD_ACT 0x800 /* CMD Active */
#define TX_ACT 0x1000 /* Transmit Active */
#define RX_ACT 0x2000 /* Receive Active */
#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
/* Bit masks for SDH_STATUS_CLR */
#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
#define DAT_END_STAT 0x100 /* Data End Status */
#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
/* Bit masks for SDH_MASK0 */
#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
#define DAT_END_MASK 0x100 /* Data End Mask */
#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
/* Bit masks for SDH_FIFO_CNT */
#define FIFO_COUNT 0x7fff /* FIFO Count */
/* Bit masks for SDH_E_STATUS */
#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
#define SD_CARD_DET 0x10 /* SD Card Detect */
/* Bit masks for SDH_E_MASK */
#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
#define SCD_MSK 0x40 /* Mask Card Detect */
/* Bit masks for SDH_CFG */
#define CLKS_EN 0x1 /* Clocks Enable */
#define SD4E 0x4 /* SDIO 4-Bit Enable */
#define MWE 0x8 /* Moving Window Enable */
#define SD_RST 0x10 /* SDMMC Reset */
#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
/* Bit masks for SDH_RD_WAIT_EN */
#define RWR 0x1 /* Read Wait Request */
/* Bit masks for ATAPI_CONTROL */
#define PIO_START 0x1 /* Start PIO/Reg Op */

152
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
View file

@ -105,15 +105,15 @@
#define TWI0_REGBASE 0xffc00700
#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
#define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */
#define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */
#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */
#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */
#define TWI0_MASTER_CTRL 0xffc00714 /* TWI Master Mode Control Register */
#define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */
#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */
#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */
#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
#define TWI0_FIFO_CTRL 0xffc00728 /* TWI FIFO Control Register */
#define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */
#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */
#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */
@ -198,8 +198,8 @@
/* DMAC0 Registers */
#define DMAC0_TCPER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
#define DMAC0_TCCNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
#define DMAC0_TC_PER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
#define DMAC0_TC_CNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
/* DMA Channel 0 Registers */
@ -688,8 +688,8 @@
/* DMAC1 Registers */
#define DMAC1_TCPER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
#define DMAC1_TCCNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
#define DMAC1_TC_PER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
#define DMAC1_TC_CNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
/* DMA Channel 12 Registers */
@ -1958,57 +1958,6 @@
#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
/* Bit masks for CNT_CONFIG */
#define CNTE 0x1 /* Counter Enable */
#define DEBE 0x2 /* Debounce Enable */
#define CDGINV 0x10 /* CDG Pin Polarity Invert */
#define CUDINV 0x20 /* CUD Pin Polarity Invert */
#define CZMINV 0x40 /* CZM Pin Polarity Invert */
#define CNTMODE 0x700 /* Counter Operating Mode */
#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
#define BNDMODE 0x3000 /* Boundary register Mode */
#define INPDIS 0x8000 /* CUG and CDG Input Disable */
/* Bit masks for CNT_IMASK */
#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
#define UCIE 0x2 /* Up count Interrupt Enable */
#define DCIE 0x4 /* Down count Interrupt Enable */
#define MINCIE 0x8 /* Min Count Interrupt Enable */
#define MAXCIE 0x10 /* Max Count Interrupt Enable */
#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
/* Bit masks for CNT_STATUS */
#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
#define UCII 0x2 /* Up count Interrupt Identifier */
#define DCII 0x4 /* Down count Interrupt Identifier */
#define MINCII 0x8 /* Min Count Interrupt Identifier */
#define MAXCII 0x10 /* Max Count Interrupt Identifier */
#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
/* Bit masks for CNT_COMMAND */
#define W1LCNT 0xf /* Load Counter Register */
#define W1LMIN 0xf0 /* Load Min Register */
#define W1LMAX 0xf00 /* Load Max Register */
#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
/* Bit masks for CNT_DEBOUNCE */
#define DPRESCALE 0xf /* Load Counter Register */
/* Bit masks for SECURE_SYSSWT */
#define EMUDABL 0x1 /* Emulation Disable. */
@ -2044,66 +1993,6 @@
#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
/* Bit masks for NFC_CTL */
#define WR_DLY 0xf /* Write Strobe Delay */
#define RD_DLY 0xf0 /* Read Strobe Delay */
#define NWIDTH 0x100 /* NAND Data Width */
#define PG_SIZE 0x200 /* Page Size */
/* Bit masks for NFC_STAT */
#define NBUSY 0x1 /* Not Busy */
#define WB_FULL 0x2 /* Write Buffer Full */
#define PG_WR_STAT 0x4 /* Page Write Pending */
#define PG_RD_STAT 0x8 /* Page Read Pending */
#define WB_EMPTY 0x10 /* Write Buffer Empty */
/* Bit masks for NFC_IRQSTAT */
#define NBUSYIRQ 0x1 /* Not Busy IRQ */
#define WB_OVF 0x2 /* Write Buffer Overflow */
#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
#define RD_RDY 0x8 /* Read Data Ready */
#define WR_DONE 0x10 /* Page Write Done */
/* Bit masks for NFC_IRQMASK */
#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
#define MASK_WRDONE 0x10 /* Mask Write Done */
/* Bit masks for NFC_RST */
#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
/* Bit masks for NFC_PGCTL */
#define PG_RD_START 0x1 /* Page Read Start */
#define PG_WR_START 0x2 /* Page Write Start */
/* Bit masks for NFC_ECC0 */
#define ECC0 0x7ff /* Parity Calculation Result0 */
/* Bit masks for NFC_ECC1 */
#define ECC1 0x7ff /* Parity Calculation Result1 */
/* Bit masks for NFC_ECC2 */
#define ECC2 0x7ff /* Parity Calculation Result2 */
/* Bit masks for NFC_ECC3 */
#define ECC3 0x7ff /* Parity Calculation Result3 */
/* Bit masks for NFC_COUNT */
#define ECCCNT 0x3ff /* Transfer Count */
/* Bit masks for EPPIx_STATUS */
#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
@ -2472,33 +2361,6 @@
#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */
#define BCODE_NOBOOT 0x0030 /* always perform full boot */
/* CNT_COMMAND bit field options */
#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
/* CNT_CONFIG bit field options */
#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
#define BNDMODE_COMP 0x0000 /* boundary compare mode */
#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
/* TMODE in TIMERx_CONFIG bit field options */
#define PWM_OUT 0x0001

10
arch/blackfin/mach-bf548/include/mach/gpio.h
View file

@ -3,6 +3,10 @@
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_GPIO_H_
#define _MACH_GPIO_H_
#define GPIO_PA0 0
#define GPIO_PA1 1
#define GPIO_PA2 2
@ -166,6 +170,8 @@
#define MAX_BLACKFIN_GPIOS 160
#ifndef __ASSEMBLY__
struct gpio_port_t {
unsigned short port_fer;
unsigned short dummy1;
@ -191,3 +197,7 @@ struct gpio_port_s {
unsigned short inen;
unsigned int mux;
};
#endif
#endif /* _MACH_GPIO_H_ */

3
arch/blackfin/mach-bf548/include/mach/portmux.h
View file

@ -7,7 +7,7 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
@ -131,6 +131,7 @@
#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PE4
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))

13
arch/blackfin/mach-bf561/include/mach/anomaly.h
View file

@ -5,7 +5,7 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2009 Analog Devices Inc.
* Copyright 2004-2010 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
@ -152,8 +152,8 @@
#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
/* NMI Event at Boot Time Results in Unpredictable State */
#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
/* Incorrect Pulse-Width of UART Start Bit */
#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
/* Scratchpad Memory Bank Reads May Return Incorrect Data */
@ -290,10 +290,14 @@
#define ANOMALY_05000461 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Core Hang With L2/L3 Configured in Writeback Cache Mode */
/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000475 (__SILICON_REVISION__ < 4)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000119 (0)
@ -319,5 +323,6 @@
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000485 (0)
#endif

96
arch/blackfin/mach-bf561/include/mach/gpio.h
View file

@ -9,54 +9,54 @@
#define MAX_BLACKFIN_GPIOS 48
#define GPIO_PF0 0
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PF16 16
#define GPIO_PF17 17
#define GPIO_PF18 18
#define GPIO_PF19 19
#define GPIO_PF20 20
#define GPIO_PF21 21
#define GPIO_PF22 22
#define GPIO_PF23 23
#define GPIO_PF24 24
#define GPIO_PF25 25
#define GPIO_PF26 26
#define GPIO_PF27 27
#define GPIO_PF28 28
#define GPIO_PF29 29
#define GPIO_PF30 30
#define GPIO_PF31 31
#define GPIO_PF32 32
#define GPIO_PF33 33
#define GPIO_PF34 34
#define GPIO_PF35 35
#define GPIO_PF36 36
#define GPIO_PF37 37
#define GPIO_PF38 38
#define GPIO_PF39 39
#define GPIO_PF40 40
#define GPIO_PF41 41
#define GPIO_PF42 42
#define GPIO_PF43 43
#define GPIO_PF44 44
#define GPIO_PF45 45
#define GPIO_PF46 46
#define GPIO_PF47 47
#define GPIO_PF0 0
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PF16 16
#define GPIO_PF17 17
#define GPIO_PF18 18
#define GPIO_PF19 19
#define GPIO_PF20 20
#define GPIO_PF21 21
#define GPIO_PF22 22
#define GPIO_PF23 23
#define GPIO_PF24 24
#define GPIO_PF25 25
#define GPIO_PF26 26
#define GPIO_PF27 27
#define GPIO_PF28 28
#define GPIO_PF29 29
#define GPIO_PF30 30
#define GPIO_PF31 31
#define GPIO_PF32 32
#define GPIO_PF33 33
#define GPIO_PF34 34
#define GPIO_PF35 35
#define GPIO_PF36 36
#define GPIO_PF37 37
#define GPIO_PF38 38
#define GPIO_PF39 39
#define GPIO_PF40 40
#define GPIO_PF41 41
#define GPIO_PF42 42
#define GPIO_PF43 43
#define GPIO_PF44 44
#define GPIO_PF45 45
#define GPIO_PF46 46
#define GPIO_PF47 47
#define PORT_FIO0 GPIO_0
#define PORT_FIO1 GPIO_16

3
arch/blackfin/mach-bf561/include/mach/portmux.h
View file

@ -7,7 +7,7 @@
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
#define P_PPI0_CLK (P_DONTCARE)
#define P_PPI0_FS1 (P_DONTCARE)
@ -91,6 +91,7 @@
#define P_SPI0_MOSI (P_DONTCARE)
#define P_SPI0_MISO (P_DONTCARE)
#define P_SPI0_SCK (P_DONTCARE)
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
#endif /* _MACH_PORTMUX_H_ */

16
arch/blackfin/mach-common/arch_checks.c
View file

@ -1,7 +1,7 @@
/*
* Do some checking to make sure things are OK
*
* Copyright 2007-2009 Analog Devices Inc.
* Copyright 2007-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
@ -47,18 +47,20 @@
# error "The kernel load address is too high; keep it below 10meg for safety"
#endif
#if ANOMALY_05000263 && defined(CONFIG_MPU)
# error the MPU will not function safely while Anomaly 05000263 applies
#endif
#if ANOMALY_05000448
# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes.
#endif
/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */
#if ANOMALY_05000220 && \
((defined(CONFIG_BFIN_EXTMEM_WRITEBACK) && !defined(CONFIG_BFIN_L2_DCACHEABLE)) || \
(!defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) && defined(CONFIG_BFIN_L2_WRITEBACK)))
# error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB.
(defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK))
# error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory"
#endif
#if ANOMALY_05000475 && \
(defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK))
# error "Anomaly 475 does not allow you to use Write Back cache with L2 or External Memory"
#if ANOMALY_05000491 && !defined(CONFIG_CACHE_FLUSH_L1)
# error You need IFLUSH in L1 inst while Anomaly 05000491 applies
#endif

15
arch/blackfin/mach-common/cache.S
View file

@ -11,7 +11,11 @@
#include <asm/cache.h>
#include <asm/page.h>
#ifdef CONFIG_CACHE_FLUSH_L1
.section .l1.text
#else
.text
#endif
/* 05000443 - IFLUSH cannot be last instruction in hardware loop */
#if ANOMALY_05000443
@ -64,17 +68,6 @@
/* Invalidate all instruction cache lines assocoiated with this memory area */
ENTRY(_blackfin_icache_flush_range)
/*
* Walkaround to avoid loading wrong instruction after invalidating icache
* and following sequence is met.
*
* 1) One instruction address is cached in the instruction cache.
* 2) This instruction in SDRAM is changed.
* 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
* 4) This instruction is executed again, but the old one is loaded.
*/
P0 = R0;
IFLUSH[P0];
do_flush IFLUSH
ENDPROC(_blackfin_icache_flush_range)

24
arch/blackfin/mach-common/dpmc_modes.S
View file

@ -17,9 +17,6 @@ ENTRY(_sleep_mode)
call _set_sic_iwr;
R0 = 0xFFFF (Z);
call _set_rtc_istat;
P0.H = hi(PLL_CTL);
P0.L = lo(PLL_CTL);
R1 = W[P0](z);
@ -65,9 +62,6 @@ ENTRY(_hibernate_mode)
call _set_dram_srfs;
SSYNC;
R0 = 0xFFFF (Z);
call _set_rtc_istat;
P0.H = hi(VR_CTL);
P0.L = lo(VR_CTL);
@ -95,9 +89,6 @@ ENTRY(_sleep_deeper)
call _set_sic_iwr;
call _set_dram_srfs; /* Set SDRAM Self Refresh */
/* Clear all the interrupts,bits sticky */
R0 = 0xFFFF (Z);
call _set_rtc_istat;
P0.H = hi(PLL_DIV);
P0.L = lo(PLL_DIV);
R6 = W[P0](z);
@ -269,21 +260,6 @@ ENTRY(_set_sic_iwr)
RTS;
ENDPROC(_set_sic_iwr)
ENTRY(_set_rtc_istat)
#ifndef CONFIG_BF561
P0.H = hi(RTC_ISTAT);
P0.L = lo(RTC_ISTAT);
w[P0] = R0.L;
SSYNC;
#elif (ANOMALY_05000371)
nop;
nop;
nop;
nop;
#endif
RTS;
ENDPROC(_set_rtc_istat)
ENTRY(_test_pll_locked)
P0.H = hi(PLL_STAT);
P0.L = lo(PLL_STAT);

17
arch/blackfin/mach-common/pm.c
View file

@ -61,10 +61,11 @@ void bfin_pm_suspend_standby_enter(void)
int bf53x_suspend_l1_mem(unsigned char *memptr)
{
dma_memcpy(memptr, (const void *) L1_CODE_START, L1_CODE_LENGTH);
dma_memcpy(memptr + L1_CODE_LENGTH, (const void *) L1_DATA_A_START,
L1_DATA_A_LENGTH);
dma_memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
dma_memcpy_nocache(memptr, (const void *) L1_CODE_START,
L1_CODE_LENGTH);
dma_memcpy_nocache(memptr + L1_CODE_LENGTH,
(const void *) L1_DATA_A_START, L1_DATA_A_LENGTH);
dma_memcpy_nocache(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
(const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
@ -75,10 +76,10 @@ int bf53x_suspend_l1_mem(unsigned char *memptr)
int bf53x_resume_l1_mem(unsigned char *memptr)
{
dma_memcpy((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
dma_memcpy((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
dma_memcpy_nocache((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
dma_memcpy_nocache((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
L1_DATA_A_LENGTH);
dma_memcpy((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
dma_memcpy_nocache((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
@ -167,7 +168,7 @@ int bfin_pm_suspend_mem_enter(void)
_disable_icplb();
bf53x_suspend_l1_mem(memptr);
do_hibernate(wakeup | vr_wakeup); /* Goodbye */
do_hibernate(wakeup | vr_wakeup); /* See you later! */
bf53x_resume_l1_mem(memptr);