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drm/radeon: implement tn_set_vce_clocks
This implements the function to set the vce clocks on TN hardware. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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b7af630c13
commit
0fda42ac40
4 changed files with 40 additions and 0 deletions
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@ -2554,3 +2554,34 @@ void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
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radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
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radeon_ring_write(ring, 0x0);
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}
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int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
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{
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struct atom_clock_dividers dividers;
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int r, i;
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r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
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ecclk, false, ÷rs);
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if (r)
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return r;
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for (i = 0; i < 100; i++) {
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if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
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break;
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mdelay(10);
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}
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if (i == 100)
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return -ETIMEDOUT;
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WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK));
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for (i = 0; i < 100; i++) {
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if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
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break;
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mdelay(10);
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}
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if (i == 100)
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return -ETIMEDOUT;
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return 0;
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}
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@ -46,6 +46,13 @@
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#define DMIF_ADDR_CONFIG 0xBD4
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/* fusion vce clocks */
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#define CG_ECLK_CNTL 0x620
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# define ECLK_DIVIDER_MASK 0x7f
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# define ECLK_DIR_CNTL_EN (1 << 8)
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#define CG_ECLK_STATUS 0x624
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# define ECLK_STATUS (1 << 0)
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/* DCE6 only */
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#define DMIF_ADDR_CALC 0xC00
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@ -1838,6 +1838,7 @@ static struct radeon_asic trinity_asic = {
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.set_pcie_lanes = NULL,
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.set_clock_gating = NULL,
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.set_uvd_clocks = &sumo_set_uvd_clocks,
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.set_vce_clocks = &tn_set_vce_clocks,
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.get_temperature = &tn_get_temp,
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},
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.dpm = {
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@ -694,6 +694,7 @@ int trinity_dpm_force_performance_level(struct radeon_device *rdev,
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void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
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u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev);
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u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev);
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int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
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/* DCE6 - SI */
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void dce6_bandwidth_update(struct radeon_device *rdev);
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