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drm/i915/skl: Update watermarks for Y tiling
Display watermarks need different programming for different tiling modes. Set the relevant flag so this happens during the plane commit and add relevant data into a structure made available to the watermark computation code. v2: Pass in tiling info to sprite plane updates as well. v3: Rebased for plane handling changes. v4: Handle fb == NULL when plane is disabled. v5: Refactored for addfb2 interface. v6: Refactored for fb modifier changes. v7: Updated for atomic commit by only updating watermarks when tiling changes. v8: BSpec watermark calculation updates. v9: Restrict scope of y_tile_minimum variable. (Damien Lespiau) v10: Get fb from plane state otherwise we are working on old state. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Acked-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Acked-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> (v9) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
parent
d4c2aa60de
commit
0fda65680e
4 changed files with 59 additions and 9 deletions
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@ -12005,6 +12005,12 @@ intel_check_primary_plane(struct drm_plane *plane,
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INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
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intel_crtc->atomic.update_fbc = true;
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/* Update watermarks on tiling changes. */
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if (!plane->state->fb || !state->base.fb ||
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plane->state->fb->modifier[0] !=
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state->base.fb->modifier[0])
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intel_crtc->atomic.update_wm = true;
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}
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return 0;
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@ -501,6 +501,7 @@ struct intel_plane_wm_parameters {
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uint8_t bytes_per_pixel;
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bool enabled;
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bool scaled;
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u64 tiling;
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};
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struct intel_plane {
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@ -2617,7 +2617,7 @@ static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
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static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
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uint32_t horiz_pixels, uint8_t bytes_per_pixel,
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uint32_t latency)
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uint64_t tiling, uint32_t latency)
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{
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uint32_t ret;
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uint32_t plane_bytes_per_line, plane_blocks_per_line;
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@ -2627,7 +2627,16 @@ static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
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return UINT_MAX;
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plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
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plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
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if (tiling == I915_FORMAT_MOD_Y_TILED ||
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tiling == I915_FORMAT_MOD_Yf_TILED) {
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plane_bytes_per_line *= 4;
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plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
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plane_blocks_per_line /= 4;
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} else {
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plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
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}
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wm_intermediate_val = latency * pixel_rate;
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ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
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plane_blocks_per_line;
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@ -2679,6 +2688,7 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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enum pipe pipe = intel_crtc->pipe;
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struct drm_plane *plane;
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struct drm_framebuffer *fb;
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int i = 1; /* Index for sprite planes start */
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p->active = intel_crtc_active(crtc);
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@ -2694,6 +2704,14 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
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crtc->primary->fb->bits_per_pixel / 8;
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p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
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p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
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p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
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fb = crtc->primary->state->fb;
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/*
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* Framebuffer can be NULL on plane disable, but it does not
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* matter for watermarks if we assume no tiling in that case.
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*/
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if (fb)
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p->plane[0].tiling = fb->modifier[0];
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p->cursor.enabled = true;
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p->cursor.bytes_per_pixel = 4;
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@ -2734,23 +2752,34 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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p->pipe_htotal,
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p_params->horiz_pixels,
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p_params->bytes_per_pixel,
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p_params->tiling,
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latency);
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plane_bytes_per_line = p_params->horiz_pixels *
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p_params->bytes_per_pixel;
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plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
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/* For now xtile and linear */
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if ((ddb_allocation / plane_blocks_per_line) >= 1)
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selected_result = min(method1, method2);
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else
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selected_result = method1;
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if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
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p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
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uint32_t y_tile_minimum = plane_blocks_per_line * 4;
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selected_result = max(method2, y_tile_minimum);
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} else {
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if ((ddb_allocation / plane_blocks_per_line) >= 1)
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selected_result = min(method1, method2);
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else
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selected_result = method1;
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}
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res_blocks = selected_result + 1;
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res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
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if (level >= 1 && level <= 7)
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res_blocks++;
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if (level >= 1 && level <= 7) {
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if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
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p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
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res_lines += 4;
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else
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res_blocks++;
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}
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if (res_blocks >= ddb_allocation || res_lines > 31)
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return false;
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@ -3179,12 +3208,20 @@ skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
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int pixel_size, bool enabled, bool scaled)
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{
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struct intel_plane *intel_plane = to_intel_plane(plane);
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struct drm_framebuffer *fb = plane->state->fb;
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intel_plane->wm.enabled = enabled;
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intel_plane->wm.scaled = scaled;
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intel_plane->wm.horiz_pixels = sprite_width;
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intel_plane->wm.vert_pixels = sprite_height;
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intel_plane->wm.bytes_per_pixel = pixel_size;
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intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
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/*
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* Framebuffer can be NULL on plane disable, but it does not
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* matter for watermarks if we assume no tiling in that case.
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*/
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if (fb)
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intel_plane->wm.tiling = fb->modifier[0];
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skl_update_wm(crtc);
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}
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@ -1256,6 +1256,12 @@ intel_check_sprite_plane(struct drm_plane *plane,
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if (!intel_crtc->primary_enabled && !state->hides_primary)
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intel_crtc->atomic.post_enable_primary = true;
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/* Update watermarks on tiling changes. */
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if (!plane->state->fb || !state->base.fb ||
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plane->state->fb->modifier[0] !=
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state->base.fb->modifier[0])
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intel_crtc->atomic.update_wm = true;
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}
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return 0;
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