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tools headers UAPI: Sync drm/i915_drm.h with the kernel sources
To pick up the changes in:ecf8eca51f("drm/i915/xehp: Add compute engine ABI")991b4de327("drm/i915/uapi: Add kerneldoc for engine class enum")c94fde8f51("drm/i915/uapi: Add DRM_I915_QUERY_GEOMETRY_SUBSLICES")1c671ad753("drm/i915/doc: Link query items to their uapi structs")a2e5402691("drm/i915/doc: Convert perf UAPI comments to kerneldoc")462ac1cdf4("drm/i915/doc: Convert drm_i915_query_topology_info comment to kerneldoc")034d47b25b("drm/i915/uapi: Document DRM_I915_QUERY_HWCONFIG_BLOB")78e1fb3112("drm/i915/uapi: Add query for hwconfig blob") That don't add any new ioctl, so no changes in tooling. This silences this perf build warning: Warning: Kernel ABI header at 'tools/include/uapi/drm/i915_drm.h' differs from latest version at 'include/uapi/drm/i915_drm.h' diff -u tools/include/uapi/drm/i915_drm.h include/uapi/drm/i915_drm.h Cc: John Harrison <John.C.Harrison@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: http://lore.kernel.org/lkml/YrDi4ALYjv9Mdocq@kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Arnaldo Carvalho de Melo
parent
342cb0d806
commit
0fdd435cb4
1 changed files with 272 additions and 81 deletions
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@ -154,25 +154,77 @@ enum i915_mocs_table_index {
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I915_MOCS_CACHED,
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};
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/*
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/**
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* enum drm_i915_gem_engine_class - uapi engine type enumeration
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*
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* Different engines serve different roles, and there may be more than one
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* engine serving each role. enum drm_i915_gem_engine_class provides a
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* classification of the role of the engine, which may be used when requesting
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* operations to be performed on a certain subset of engines, or for providing
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* information about that group.
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* engine serving each role. This enum provides a classification of the role
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* of the engine, which may be used when requesting operations to be performed
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* on a certain subset of engines, or for providing information about that
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* group.
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*/
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enum drm_i915_gem_engine_class {
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/**
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* @I915_ENGINE_CLASS_RENDER:
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*
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* Render engines support instructions used for 3D, Compute (GPGPU),
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* and programmable media workloads. These instructions fetch data and
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* dispatch individual work items to threads that operate in parallel.
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* The threads run small programs (called "kernels" or "shaders") on
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* the GPU's execution units (EUs).
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*/
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I915_ENGINE_CLASS_RENDER = 0,
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/**
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* @I915_ENGINE_CLASS_COPY:
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*
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* Copy engines (also referred to as "blitters") support instructions
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* that move blocks of data from one location in memory to another,
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* or that fill a specified location of memory with fixed data.
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* Copy engines can perform pre-defined logical or bitwise operations
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* on the source, destination, or pattern data.
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*/
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I915_ENGINE_CLASS_COPY = 1,
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/**
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* @I915_ENGINE_CLASS_VIDEO:
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*
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* Video engines (also referred to as "bit stream decode" (BSD) or
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* "vdbox") support instructions that perform fixed-function media
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* decode and encode.
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*/
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I915_ENGINE_CLASS_VIDEO = 2,
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/**
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* @I915_ENGINE_CLASS_VIDEO_ENHANCE:
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*
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* Video enhancement engines (also referred to as "vebox") support
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* instructions related to image enhancement.
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*/
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I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
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/* should be kept compact */
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/**
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* @I915_ENGINE_CLASS_COMPUTE:
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*
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* Compute engines support a subset of the instructions available
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* on render engines: compute engines support Compute (GPGPU) and
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* programmable media workloads, but do not support the 3D pipeline.
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*/
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I915_ENGINE_CLASS_COMPUTE = 4,
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/* Values in this enum should be kept compact. */
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/**
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* @I915_ENGINE_CLASS_INVALID:
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*
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* Placeholder value to represent an invalid engine class assignment.
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*/
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I915_ENGINE_CLASS_INVALID = -1
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};
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/*
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/**
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* struct i915_engine_class_instance - Engine class/instance identifier
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*
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* There may be more than one engine fulfilling any role within the system.
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* Each engine of a class is given a unique instance number and therefore
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* any engine can be specified by its class:instance tuplet. APIs that allow
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@ -180,10 +232,21 @@ enum drm_i915_gem_engine_class {
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* for this identification.
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*/
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struct i915_engine_class_instance {
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__u16 engine_class; /* see enum drm_i915_gem_engine_class */
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__u16 engine_instance;
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/**
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* @engine_class:
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*
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* Engine class from enum drm_i915_gem_engine_class
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*/
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__u16 engine_class;
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#define I915_ENGINE_CLASS_INVALID_NONE -1
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#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
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/**
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* @engine_instance:
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*
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* Engine instance.
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*/
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__u16 engine_instance;
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};
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/**
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@ -2657,24 +2720,65 @@ enum drm_i915_perf_record_type {
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DRM_I915_PERF_RECORD_MAX /* non-ABI */
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};
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/*
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/**
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* struct drm_i915_perf_oa_config
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*
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* Structure to upload perf dynamic configuration into the kernel.
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*/
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struct drm_i915_perf_oa_config {
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/** String formatted like "%08x-%04x-%04x-%04x-%012x" */
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/**
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* @uuid:
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*
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* String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"
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*/
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char uuid[36];
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/**
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* @n_mux_regs:
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*
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* Number of mux regs in &mux_regs_ptr.
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*/
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__u32 n_mux_regs;
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/**
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* @n_boolean_regs:
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*
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* Number of boolean regs in &boolean_regs_ptr.
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*/
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__u32 n_boolean_regs;
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/**
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* @n_flex_regs:
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*
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* Number of flex regs in &flex_regs_ptr.
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*/
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__u32 n_flex_regs;
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/*
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* These fields are pointers to tuples of u32 values (register address,
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* value). For example the expected length of the buffer pointed by
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* mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
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/**
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* @mux_regs_ptr:
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*
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* Pointer to tuples of u32 values (register address, value) for mux
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* registers. Expected length of buffer is (2 * sizeof(u32) *
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* &n_mux_regs).
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*/
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__u64 mux_regs_ptr;
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/**
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* @boolean_regs_ptr:
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*
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* Pointer to tuples of u32 values (register address, value) for mux
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* registers. Expected length of buffer is (2 * sizeof(u32) *
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* &n_boolean_regs).
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*/
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__u64 boolean_regs_ptr;
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/**
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* @flex_regs_ptr:
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*
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* Pointer to tuples of u32 values (register address, value) for mux
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* registers. Expected length of buffer is (2 * sizeof(u32) *
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* &n_flex_regs).
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*/
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__u64 flex_regs_ptr;
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};
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@ -2685,12 +2789,24 @@ struct drm_i915_perf_oa_config {
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* @data_ptr is also depends on the specific @query_id.
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*/
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struct drm_i915_query_item {
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/** @query_id: The id for this query */
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/**
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* @query_id:
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*
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* The id for this query. Currently accepted query IDs are:
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* - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info)
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* - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info)
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* - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config)
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* - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions)
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* - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`)
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* - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info)
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*/
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__u64 query_id;
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#define DRM_I915_QUERY_TOPOLOGY_INFO 1
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#define DRM_I915_QUERY_ENGINE_INFO 2
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#define DRM_I915_QUERY_PERF_CONFIG 3
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#define DRM_I915_QUERY_MEMORY_REGIONS 4
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#define DRM_I915_QUERY_TOPOLOGY_INFO 1
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#define DRM_I915_QUERY_ENGINE_INFO 2
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#define DRM_I915_QUERY_PERF_CONFIG 3
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#define DRM_I915_QUERY_MEMORY_REGIONS 4
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#define DRM_I915_QUERY_HWCONFIG_BLOB 5
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#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
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/* Must be kept compact -- no holes and well documented */
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/**
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@ -2706,14 +2822,17 @@ struct drm_i915_query_item {
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/**
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* @flags:
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*
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* When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
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* When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
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*
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* When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
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* When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the
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* following:
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*
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* - DRM_I915_QUERY_PERF_CONFIG_LIST
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* - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
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* - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
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* - %DRM_I915_QUERY_PERF_CONFIG_LIST
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* - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
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* - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
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*
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* When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain
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* a struct i915_engine_class_instance that references a render engine.
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*/
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__u32 flags;
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#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
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@ -2771,66 +2890,112 @@ struct drm_i915_query {
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__u64 items_ptr;
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};
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/*
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* Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
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/**
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* struct drm_i915_query_topology_info
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*
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* data: contains the 3 pieces of information :
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*
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* - the slice mask with one bit per slice telling whether a slice is
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* available. The availability of slice X can be queried with the following
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* formula :
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*
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* (data[X / 8] >> (X % 8)) & 1
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*
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* - the subslice mask for each slice with one bit per subslice telling
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* whether a subslice is available. Gen12 has dual-subslices, which are
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* similar to two gen11 subslices. For gen12, this array represents dual-
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* subslices. The availability of subslice Y in slice X can be queried
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* with the following formula :
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*
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* (data[subslice_offset +
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* X * subslice_stride +
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* Y / 8] >> (Y % 8)) & 1
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*
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* - the EU mask for each subslice in each slice with one bit per EU telling
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* whether an EU is available. The availability of EU Z in subslice Y in
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* slice X can be queried with the following formula :
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*
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* (data[eu_offset +
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* (X * max_subslices + Y) * eu_stride +
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* Z / 8] >> (Z % 8)) & 1
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* Describes slice/subslice/EU information queried by
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* %DRM_I915_QUERY_TOPOLOGY_INFO
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*/
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struct drm_i915_query_topology_info {
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/*
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/**
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* @flags:
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*
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* Unused for now. Must be cleared to zero.
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*/
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__u16 flags;
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/**
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* @max_slices:
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*
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* The number of bits used to express the slice mask.
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*/
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__u16 max_slices;
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/**
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* @max_subslices:
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*
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* The number of bits used to express the subslice mask.
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*/
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__u16 max_subslices;
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/**
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* @max_eus_per_subslice:
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*
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* The number of bits in the EU mask that correspond to a single
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* subslice's EUs.
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*/
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__u16 max_eus_per_subslice;
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/*
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/**
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* @subslice_offset:
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*
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* Offset in data[] at which the subslice masks are stored.
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*/
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__u16 subslice_offset;
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/*
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/**
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* @subslice_stride:
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*
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* Stride at which each of the subslice masks for each slice are
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* stored.
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*/
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__u16 subslice_stride;
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/*
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/**
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* @eu_offset:
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*
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* Offset in data[] at which the EU masks are stored.
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*/
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__u16 eu_offset;
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/*
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/**
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* @eu_stride:
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*
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* Stride at which each of the EU masks for each subslice are stored.
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*/
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__u16 eu_stride;
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/**
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* @data:
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*
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* Contains 3 pieces of information :
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*
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* - The slice mask with one bit per slice telling whether a slice is
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* available. The availability of slice X can be queried with the
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* following formula :
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*
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* .. code:: c
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*
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* (data[X / 8] >> (X % 8)) & 1
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*
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* Starting with Xe_HP platforms, Intel hardware no longer has
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* traditional slices so i915 will always report a single slice
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* (hardcoded slicemask = 0x1) which contains all of the platform's
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* subslices. I.e., the mask here does not reflect any of the newer
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* hardware concepts such as "gslices" or "cslices" since userspace
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* is capable of inferring those from the subslice mask.
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*
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* - The subslice mask for each slice with one bit per subslice telling
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* whether a subslice is available. Starting with Gen12 we use the
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* term "subslice" to refer to what the hardware documentation
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* describes as a "dual-subslices." The availability of subslice Y
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* in slice X can be queried with the following formula :
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*
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* .. code:: c
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*
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* (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1
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*
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* - The EU mask for each subslice in each slice, with one bit per EU
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* telling whether an EU is available. The availability of EU Z in
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* subslice Y in slice X can be queried with the following formula :
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*
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* .. code:: c
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*
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* (data[eu_offset +
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* (X * max_subslices + Y) * eu_stride +
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* Z / 8
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* ] >> (Z % 8)) & 1
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*/
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__u8 data[];
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};
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@ -2951,52 +3116,68 @@ struct drm_i915_query_engine_info {
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struct drm_i915_engine_info engines[];
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};
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/*
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* Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
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/**
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* struct drm_i915_query_perf_config
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*
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* Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and
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* %DRM_I915_QUERY_GEOMETRY_SUBSLICES.
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*/
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struct drm_i915_query_perf_config {
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union {
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/*
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* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
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* this fields to the number of configurations available.
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/**
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* @n_configs:
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*
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* When &drm_i915_query_item.flags ==
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* %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to
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* the number of configurations available.
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*/
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__u64 n_configs;
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/*
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* When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
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* i915 will use the value in this field as configuration
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* identifier to decide what data to write into config_ptr.
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/**
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* @config:
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*
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* When &drm_i915_query_item.flags ==
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* %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the
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* value in this field as configuration identifier to decide
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* what data to write into config_ptr.
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*/
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__u64 config;
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/*
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* When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
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* i915 will use the value in this field as configuration
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* identifier to decide what data to write into config_ptr.
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/**
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* @uuid:
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*
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* When &drm_i915_query_item.flags ==
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* %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the
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* value in this field as configuration identifier to decide
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* what data to write into config_ptr.
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*
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* String formatted like "%08x-%04x-%04x-%04x-%012x"
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*/
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char uuid[36];
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};
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/*
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/**
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* @flags:
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*
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* Unused for now. Must be cleared to zero.
|
||||
*/
|
||||
__u32 flags;
|
||||
|
||||
/*
|
||||
* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
|
||||
* write an array of __u64 of configuration identifiers.
|
||||
/**
|
||||
* @data:
|
||||
*
|
||||
* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
|
||||
* write a struct drm_i915_perf_oa_config. If the following fields of
|
||||
* drm_i915_perf_oa_config are set not set to 0, i915 will write into
|
||||
* the associated pointers the values of submitted when the
|
||||
* When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST,
|
||||
* i915 will write an array of __u64 of configuration identifiers.
|
||||
*
|
||||
* When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA,
|
||||
* i915 will write a struct drm_i915_perf_oa_config. If the following
|
||||
* fields of struct drm_i915_perf_oa_config are not set to 0, i915 will
|
||||
* write into the associated pointers the values of submitted when the
|
||||
* configuration was created :
|
||||
*
|
||||
* - n_mux_regs
|
||||
* - n_boolean_regs
|
||||
* - n_flex_regs
|
||||
* - &drm_i915_perf_oa_config.n_mux_regs
|
||||
* - &drm_i915_perf_oa_config.n_boolean_regs
|
||||
* - &drm_i915_perf_oa_config.n_flex_regs
|
||||
*/
|
||||
__u8 data[];
|
||||
};
|
||||
|
|
@ -3134,6 +3315,16 @@ struct drm_i915_query_memory_regions {
|
|||
struct drm_i915_memory_region_info regions[];
|
||||
};
|
||||
|
||||
/**
|
||||
* DOC: GuC HWCONFIG blob uAPI
|
||||
*
|
||||
* The GuC produces a blob with information about the current device.
|
||||
* i915 reads this blob from GuC and makes it available via this uAPI.
|
||||
*
|
||||
* The format and meaning of the blob content are documented in the
|
||||
* Programmer's Reference Manual.
|
||||
*/
|
||||
|
||||
/**
|
||||
* struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
|
||||
* extension support using struct i915_user_extension.
|
||||
|
|
|
|||
Loading…
Reference in a new issue