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[MIPS] Use MIPS R2 instructions for bitops.
Add R2 optimized variants of clear_bit, set_bit and test_and_clear_bit. With gcc 4.1.1 this saves 1592 bytes on a defconfig (minus IPv6) kernel. Turns out that R2 bitop instructions are no gain for the other bitop functions. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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151fd6acd9
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1 changed files with 51 additions and 1 deletions
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@ -3,7 +3,7 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 1994 - 1997, 1999, 2000, 06 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (c) 1994 - 1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (c) 1999, 2000 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_BITOPS_H
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@ -24,11 +24,15 @@
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#define SZLONG_MASK 31UL
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#define __LL "ll "
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#define __SC "sc "
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#define __INS "ins "
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#define __EXT "ext "
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#elif (_MIPS_SZLONG == 64)
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#define SZLONG_LOG 6
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#define SZLONG_MASK 63UL
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#define __LL "lld "
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#define __SC "scd "
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#define __INS "dins "
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#define __EXT "dext "
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#endif
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/*
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@ -62,6 +66,19 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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#ifdef CONFIG_CPU_MIPSR2
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} else if (__builtin_constant_p(nr)) {
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__asm__ __volatile__(
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"1: " __LL "%0, %1 # set_bit \n"
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" " __INS "%0, %4, %2, 1 \n"
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" " __SC "%0, %1 \n"
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" beqz %0, 2f \n"
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" .subsection 2 \n"
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"2: b 1b \n"
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" .previous \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (nr & SZLONG_MASK), "m" (*m), "r" (~0));
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#endif /* CONFIG_CPU_MIPSR2 */
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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" .set mips3 \n"
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@ -113,6 +130,19 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
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#ifdef CONFIG_CPU_MIPSR2
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} else if (__builtin_constant_p(nr)) {
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__asm__ __volatile__(
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"1: " __LL "%0, %1 # clear_bit \n"
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" " __INS "%0, $0, %2, 1 \n"
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" " __SC "%0, %1 \n"
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" beqz %0, 2f \n"
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" .subsection 2 \n"
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"2: b 1b \n"
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" .previous \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (nr & SZLONG_MASK), "m" (*m));
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#endif /* CONFIG_CPU_MIPSR2 */
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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" .set mips3 \n"
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@ -291,6 +321,26 @@ static inline int test_and_clear_bit(unsigned long nr,
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: "memory");
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return res != 0;
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#ifdef CONFIG_CPU_MIPSR2
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} else if (__builtin_constant_p(nr)) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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__asm__ __volatile__(
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"1: " __LL "%0, %1 # test_and_clear_bit \n"
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" " __EXT "%2, %0, %3, 1 \n"
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" " __INS "%0, $0, %3, 1 \n"
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" " __SC "%0, %1 \n"
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" beqz %0, 2f \n"
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" .subsection 2 \n"
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"2: b 1b \n"
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" .previous \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "ri" (nr & SZLONG_MASK), "m" (*m)
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: "memory");
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return res;
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#endif
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} else if (cpu_has_llsc) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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