MIPS: Retire MACH_PISTACHIO
Now it can be replaced by generic kernel. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Jiaxun Yang
Thomas Bogendoerfer
parent
917b64f1df
commit
104f942b28
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@ -21,7 +21,6 @@ platform-$(CONFIG_MIPS_MALTA) += mti-malta/
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platform-$(CONFIG_MACH_NINTENDO64) += n64/
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platform-$(CONFIG_NLM_COMMON) += netlogic/
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platform-$(CONFIG_PIC32MZDA) += pic32/
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platform-$(CONFIG_MACH_PISTACHIO) += pistachio/
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platform-$(CONFIG_RALINK) += ralink/
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platform-$(CONFIG_MIKROTIK_RB532) += rb532/
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platform-$(CONFIG_SGI_IP22) += sgi-ip22/
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@ -513,35 +513,6 @@ config MACH_LOONGSON64
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and Loongson-2F which will be removed), developed by the Institute
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of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
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config MACH_PISTACHIO
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bool "IMG Pistachio SoC based boards"
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select BOOT_ELF32
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select BOOT_RAW
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select CEVT_R4K
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select CLKSRC_MIPS_GIC
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select COMMON_CLK
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select CSRC_R4K
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select DMA_NONCOHERENT
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select GPIOLIB
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select IRQ_MIPS_CPU
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select MFD_SYSCON
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select MIPS_CPU_SCACHE
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select MIPS_GIC
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select PINCTRL
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select REGULATOR
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select SYS_HAS_CPU_MIPS32_R2
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_SUPPORTS_MIPS_CPS
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select SYS_SUPPORTS_MULTITHREADING
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select SYS_SUPPORTS_RELOCATABLE
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select SYS_SUPPORTS_ZBOOT
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select SYS_HAS_EARLY_PRINTK
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select USE_GENERIC_EARLY_PRINTK_8250
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select USE_OF
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help
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This enables support for the IMG Pistachio SoC platform.
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config MIPS_MALTA
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bool "MIPS Malta board"
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select ARCH_MAY_HAVE_PC_FDC
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@ -1088,7 +1059,6 @@ source "arch/mips/ingenic/Kconfig"
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source "arch/mips/jazz/Kconfig"
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source "arch/mips/lantiq/Kconfig"
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source "arch/mips/pic32/Kconfig"
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source "arch/mips/pistachio/Kconfig"
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source "arch/mips/ralink/Kconfig"
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source "arch/mips/sgi-ip27/Kconfig"
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source "arch/mips/sibyte/Kconfig"
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@ -1,7 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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subdir-$(CONFIG_BMIPS_GENERIC) += brcm
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subdir-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon
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subdir-$(CONFIG_MACH_PISTACHIO) += img
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subdir-$(CONFIG_FIT_IMAGE_FDT_MARDUK) += img
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subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img
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subdir-$(CONFIG_MACH_INGENIC) += ingenic
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@ -2,6 +2,3 @@
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dtb-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += boston.dtb
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dtb-$(CONFIG_FIT_IMAGE_FDT_MARDUK) += pistachio_marduk.dtb
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dtb-$(CONFIG_MACH_PISTACHIO) += pistachio_marduk.dtb
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obj-$(CONFIG_MACH_PISTACHIO) += pistachio_marduk.dtb.o
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@ -1,316 +0,0 @@
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# CONFIG_LOCALVERSION_AUTO is not set
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CONFIG_DEFAULT_HOSTNAME="localhost"
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CONFIG_SYSVIPC=y
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CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_PREEMPT_VOLUNTARY=y
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CONFIG_IKCONFIG=m
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CONFIG_IKCONFIG_PROC=y
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CONFIG_LOG_BUF_SHIFT=18
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CONFIG_CGROUPS=y
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CONFIG_CGROUP_SCHED=y
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CONFIG_CFS_BANDWIDTH=y
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CONFIG_CGROUP_FREEZER=y
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CONFIG_NAMESPACES=y
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CONFIG_USER_NS=y
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CONFIG_BLK_DEV_INITRD=y
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# CONFIG_RD_BZIP2 is not set
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# CONFIG_RD_LZMA is not set
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# CONFIG_RD_LZO is not set
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# CONFIG_RD_LZ4 is not set
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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CONFIG_EMBEDDED=y
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# CONFIG_COMPAT_BRK is not set
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CONFIG_PROFILING=y
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CONFIG_MACH_PISTACHIO=y
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CONFIG_MIPS_CPS=y
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CONFIG_NR_CPUS=4
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CONFIG_PM_DEBUG=y
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CONFIG_PM_ADVANCED_DEBUG=y
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CONFIG_CPU_IDLE=y
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# CONFIG_MIPS_CPS_CPUIDLE is not set
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_MODULE_FORCE_UNLOAD=y
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CONFIG_PARTITION_ADVANCED=y
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# CONFIG_COMPACTION is not set
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CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
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CONFIG_ZSMALLOC=y
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_NET_KEY=m
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CONFIG_INET=y
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CONFIG_IP_MULTICAST=y
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CONFIG_IP_ADVANCED_ROUTER=y
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CONFIG_IP_MULTIPLE_TABLES=y
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CONFIG_IP_ROUTE_MULTIPATH=y
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CONFIG_IP_ROUTE_VERBOSE=y
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CONFIG_IP_PNP=y
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CONFIG_IP_PNP_DHCP=y
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CONFIG_IP_MROUTE=y
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CONFIG_IP_PIMSM_V1=y
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CONFIG_IP_PIMSM_V2=y
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CONFIG_SYN_COOKIES=y
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CONFIG_INET_AH=m
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CONFIG_INET_ESP=m
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CONFIG_INET_IPCOMP=m
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CONFIG_INET_XFRM_MODE_TRANSPORT=m
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CONFIG_INET_XFRM_MODE_TUNNEL=m
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CONFIG_INET_XFRM_MODE_BEET=m
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# CONFIG_INET_DIAG is not set
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CONFIG_TCP_CONG_ADVANCED=y
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# CONFIG_TCP_CONG_BIC is not set
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# CONFIG_TCP_CONG_WESTWOOD is not set
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# CONFIG_TCP_CONG_HTCP is not set
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CONFIG_TCP_CONG_LP=m
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CONFIG_TCP_MD5SIG=y
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CONFIG_INET6_AH=m
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CONFIG_INET6_ESP=m
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CONFIG_INET6_XFRM_MODE_TRANSPORT=m
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CONFIG_INET6_XFRM_MODE_TUNNEL=m
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CONFIG_INET6_XFRM_MODE_BEET=m
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CONFIG_IPV6_SIT=m
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CONFIG_NETWORK_SECMARK=y
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CONFIG_NETFILTER=y
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# CONFIG_BRIDGE_NETFILTER is not set
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CONFIG_NF_CONNTRACK=y
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CONFIG_NF_CT_NETLINK=y
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CONFIG_NETFILTER_XT_MARK=m
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CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
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CONFIG_NETFILTER_XT_TARGET_DSCP=y
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CONFIG_NETFILTER_XT_TARGET_NFLOG=y
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CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
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CONFIG_NETFILTER_XT_TARGET_SECMARK=y
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CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
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CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
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CONFIG_NETFILTER_XT_MATCH_DSCP=y
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CONFIG_NETFILTER_XT_MATCH_POLICY=y
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CONFIG_NETFILTER_XT_MATCH_STATE=y
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CONFIG_NF_NAT_IPV4=m
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CONFIG_IP_NF_IPTABLES=y
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CONFIG_IP_NF_FILTER=y
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CONFIG_IP_NF_TARGET_REJECT=y
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CONFIG_IP_NF_MANGLE=y
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CONFIG_NF_NAT_IPV6=m
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CONFIG_IP6_NF_IPTABLES=m
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CONFIG_IP6_NF_MATCH_IPV6HEADER=m
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CONFIG_IP6_NF_FILTER=m
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CONFIG_IP6_NF_TARGET_REJECT=m
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CONFIG_IP6_NF_MANGLE=m
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CONFIG_BRIDGE=m
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CONFIG_VLAN_8021Q=m
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CONFIG_NET_SCHED=y
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CONFIG_NET_SCH_HTB=m
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CONFIG_NET_SCH_CODEL=m
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CONFIG_NET_SCH_FQ_CODEL=m
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CONFIG_NET_CLS_U32=m
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CONFIG_CLS_U32_MARK=y
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CONFIG_BT=m
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CONFIG_BT_RFCOMM=m
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CONFIG_BT_HCIBTUSB=m
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CONFIG_BT_HCIBFUSB=m
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CONFIG_BT_HCIVHCI=m
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CONFIG_CFG80211=m
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CONFIG_NL80211_TESTMODE=y
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CONFIG_CFG80211_DEBUGFS=y
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CONFIG_CFG80211_WEXT=y
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CONFIG_MAC80211=m
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CONFIG_MAC80211_LEDS=y
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CONFIG_MAC80211_DEBUGFS=y
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CONFIG_MAC80211_DEBUG_MENU=y
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CONFIG_MAC80211_VERBOSE_DEBUG=y
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CONFIG_RFKILL=y
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CONFIG_DEVTMPFS=y
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CONFIG_DEVTMPFS_MOUNT=y
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CONFIG_DEBUG_DEVRES=y
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CONFIG_CONNECTOR=y
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CONFIG_MTD=y
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CONFIG_MTD_BLOCK=y
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CONFIG_MTD_SPI_NOR=y
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CONFIG_MTD_UBI=y
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CONFIG_MTD_UBI_BLOCK=y
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CONFIG_ZRAM=m
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_SCSI=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLK_DEV_SR=m
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CONFIG_SCSI_SPI_ATTRS=y
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CONFIG_MD=y
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CONFIG_BLK_DEV_DM=y
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CONFIG_DM_CRYPT=y
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CONFIG_DM_VERITY=y
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CONFIG_NETDEVICES=y
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CONFIG_TUN=m
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CONFIG_VETH=m
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# CONFIG_NET_VENDOR_MARVELL is not set
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# CONFIG_NET_VENDOR_MICREL is not set
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# CONFIG_NET_VENDOR_MICROCHIP is not set
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# CONFIG_NET_VENDOR_NATSEMI is not set
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# CONFIG_NET_VENDOR_SEEQ is not set
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# CONFIG_NET_VENDOR_SMSC is not set
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CONFIG_STMMAC_ETH=y
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# CONFIG_NET_VENDOR_VIA is not set
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CONFIG_PPP=m
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CONFIG_PPP_ASYNC=m
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CONFIG_USB_PEGASUS=m
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CONFIG_USB_RTL8150=m
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CONFIG_USB_RTL8152=m
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CONFIG_USB_NET_DM9601=m
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CONFIG_USB_NET_SMSC75XX=m
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CONFIG_USB_NET_SMSC95XX=m
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CONFIG_USB_NET_MCS7830=m
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# CONFIG_USB_NET_CDC_SUBSET is not set
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# CONFIG_USB_NET_ZAURUS is not set
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CONFIG_HOSTAP=m
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CONFIG_HOSTAP_FIRMWARE=y
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CONFIG_HOSTAP_FIRMWARE_NVRAM=y
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CONFIG_LIBERTAS_THINFIRM=m
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CONFIG_RT2X00=m
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CONFIG_RT2800USB=m
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CONFIG_MAC80211_HWSIM=m
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CONFIG_USB_NET_RNDIS_WLAN=m
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CONFIG_INPUT_EVDEV=y
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# CONFIG_KEYBOARD_ATKBD is not set
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CONFIG_KEYBOARD_GPIO=y
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# CONFIG_INPUT_MOUSE is not set
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# CONFIG_SERIO is not set
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# CONFIG_VT is not set
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# CONFIG_LEGACY_PTYS is not set
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CONFIG_SERIAL_8250=y
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# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_DW=y
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CONFIG_SERIAL_OF_PLATFORM=y
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CONFIG_HW_RANDOM=y
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CONFIG_TCG_TPM=y
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CONFIG_I2C=y
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CONFIG_I2C_CHARDEV=m
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CONFIG_I2C_IMG=y
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CONFIG_I2C_STUB=m
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CONFIG_SPI=y
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CONFIG_SPI_BITBANG=m
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CONFIG_SPI_IMG_SPFI=y
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CONFIG_SPI_SPIDEV=y
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CONFIG_DEBUG_GPIO=y
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CONFIG_GPIO_SYSFS=y
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CONFIG_POWER_SUPPLY=y
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CONFIG_THERMAL=y
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CONFIG_WATCHDOG=y
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CONFIG_IMGPDC_WDT=y
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CONFIG_REGULATOR_FIXED_VOLTAGE=y
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CONFIG_REGULATOR_GPIO=y
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CONFIG_RC_CORE=y
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CONFIG_RC_DEVICES=y
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CONFIG_IR_IMG=y
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CONFIG_IR_IMG_NEC=y
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CONFIG_IR_IMG_JVC=y
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CONFIG_IR_IMG_SONY=y
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CONFIG_IR_IMG_SHARP=y
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CONFIG_IR_IMG_SANYO=y
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CONFIG_IR_IMG_RC5=y
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CONFIG_IR_IMG_RC6=y
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CONFIG_MEDIA_SUPPORT=y
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CONFIG_FB=y
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CONFIG_FB_MODE_HELPERS=y
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# CONFIG_LCD_CLASS_DEVICE is not set
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CONFIG_BACKLIGHT_CLASS_DEVICE=y
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CONFIG_SOUND=y
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CONFIG_SND=y
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CONFIG_SND_HRTIMER=m
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CONFIG_SND_DYNAMIC_MINORS=y
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CONFIG_SND_SEQUENCER=m
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CONFIG_SND_SEQ_DUMMY=m
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# CONFIG_SND_SPI is not set
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CONFIG_SND_USB_AUDIO=m
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CONFIG_USB=y
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CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
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# CONFIG_USB_DEFAULT_PERSIST is not set
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CONFIG_USB_MON=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_ROOT_HUB_TT=y
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CONFIG_USB_ACM=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_DWC2=y
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CONFIG_USB_SERIAL=y
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CONFIG_USB_SERIAL_GENERIC=y
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CONFIG_USB_SERIAL_CP210X=m
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CONFIG_USB_SERIAL_FTDI_SIO=m
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CONFIG_USB_SERIAL_KEYSPAN=m
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CONFIG_USB_SERIAL_PL2303=m
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CONFIG_USB_SERIAL_OTI6858=m
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CONFIG_USB_SERIAL_QUALCOMM=m
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CONFIG_USB_SERIAL_SIERRAWIRELESS=m
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CONFIG_USB_SERIAL_OPTION=m
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CONFIG_MMC=y
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CONFIG_MMC_BLOCK_MINORS=16
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CONFIG_MMC_TEST=m
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CONFIG_MMC_DW=y
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CONFIG_NEW_LEDS=y
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CONFIG_LEDS_CLASS=y
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CONFIG_RTC_CLASS=y
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CONFIG_DMADEVICES=y
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CONFIG_IMG_MDC_DMA=y
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CONFIG_STAGING=y
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CONFIG_ASHMEM=y
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# CONFIG_IOMMU_SUPPORT is not set
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CONFIG_MEMORY=y
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CONFIG_IIO=y
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CONFIG_CC10001_ADC=y
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CONFIG_PWM=y
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CONFIG_PWM_IMG=y
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CONFIG_PHY_PISTACHIO_USB=y
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CONFIG_ANDROID=y
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CONFIG_EXT4_FS=y
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CONFIG_EXT4_FS_POSIX_ACL=y
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CONFIG_EXT4_FS_SECURITY=y
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# CONFIG_DNOTIFY is not set
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CONFIG_FUSE_FS=m
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CONFIG_ISO9660_FS=m
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CONFIG_JOLIET=y
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CONFIG_ZISOFS=y
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CONFIG_UDF_FS=m
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CONFIG_VFAT_FS=m
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CONFIG_TMPFS=y
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CONFIG_TMPFS_POSIX_ACL=y
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CONFIG_ECRYPT_FS=y
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CONFIG_HFSPLUS_FS=m
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CONFIG_UBIFS_FS=y
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CONFIG_SQUASHFS=y
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CONFIG_SQUASHFS_FILE_DIRECT=y
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CONFIG_SQUASHFS_LZO=y
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CONFIG_PSTORE=y
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CONFIG_PSTORE_CONSOLE=y
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CONFIG_PSTORE_RAM=y
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CONFIG_NFS_FS=y
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CONFIG_ROOT_NFS=y
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CONFIG_NLS_DEFAULT="utf8"
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CONFIG_NLS_CODEPAGE_437=m
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CONFIG_NLS_ASCII=m
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CONFIG_NLS_ISO8859_1=m
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CONFIG_SECURITY=y
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CONFIG_SECURITY_NETWORK=y
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CONFIG_SECURITY_YAMA=y
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CONFIG_CRYPTO_AUTHENC=y
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CONFIG_CRYPTO_HMAC=y
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CONFIG_CRYPTO_SHA1=y
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CONFIG_CRYPTO_SHA256=y
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CONFIG_CRYPTO_SHA512=m
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CONFIG_CRYPTO_ARC4=y
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CONFIG_CRYPTO_DES=y
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CONFIG_CRC_CCITT=y
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CONFIG_CRC_T10DIF=m
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CONFIG_CRC7=m
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# CONFIG_XZ_DEC_X86 is not set
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CONFIG_PRINTK_TIME=y
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CONFIG_DEBUG_INFO=y
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CONFIG_MAGIC_SYSRQ=y
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CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0
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# CONFIG_SCHED_DEBUG is not set
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CONFIG_SCHEDSTATS=y
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CONFIG_DEBUG_SPINLOCK=y
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CONFIG_DEBUG_CREDENTIALS=y
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CONFIG_FUNCTION_TRACER=y
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CONFIG_BLK_DEV_IO_TRACE=y
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CONFIG_LKDTM=y
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CONFIG_TEST_UDELAY=m
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@ -1,14 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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config PISTACHIO_GPTIMER_CLKSRC
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bool "Enable General Purpose Timer based clocksource"
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depends on MACH_PISTACHIO
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select CLKSRC_PISTACHIO
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select MIPS_EXTERNAL_TIMER
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help
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This option enables a clocksource driver based on a Pistachio
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SoC General Purpose external timer.
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If you want to enable the CPUFreq, you need to enable
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this option.
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If you don't want to enable CPUFreq, you can leave this disabled.
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@ -1,2 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-y += init.o irq.o time.o
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@ -1,6 +0,0 @@
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#
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# IMG Pistachio SoC
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#
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load-$(CONFIG_MACH_PISTACHIO) += 0xffffffff80400000
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zload-$(CONFIG_MACH_PISTACHIO) += 0xffffffff81000000
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all-$(CONFIG_MACH_PISTACHIO) := uImage.gz
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@ -1,125 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Pistachio platform setup
|
||||
*
|
||||
* Copyright (C) 2014 Google, Inc.
|
||||
* Copyright (C) 2016 Imagination Technologies
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_fdt.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/fw/fw.h>
|
||||
#include <asm/mips-boards/generic.h>
|
||||
#include <asm/mips-cps.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/smp-ops.h>
|
||||
#include <asm/traps.h>
|
||||
|
||||
/*
|
||||
* Core revision register decoding
|
||||
* Bits 23 to 20: Major rev
|
||||
* Bits 15 to 8: Minor rev
|
||||
* Bits 7 to 0: Maintenance rev
|
||||
*/
|
||||
#define PISTACHIO_CORE_REV_REG 0xB81483D0
|
||||
#define PISTACHIO_CORE_REV_A1 0x00100006
|
||||
#define PISTACHIO_CORE_REV_B0 0x00100106
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
u32 core_rev;
|
||||
const char *sys_type;
|
||||
|
||||
core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG);
|
||||
|
||||
switch (core_rev) {
|
||||
case PISTACHIO_CORE_REV_B0:
|
||||
sys_type = "IMG Pistachio SoC (B0)";
|
||||
break;
|
||||
|
||||
case PISTACHIO_CORE_REV_A1:
|
||||
sys_type = "IMG Pistachio SoC (A1)";
|
||||
break;
|
||||
|
||||
default:
|
||||
sys_type = "IMG Pistachio SoC";
|
||||
break;
|
||||
}
|
||||
|
||||
return sys_type;
|
||||
}
|
||||
|
||||
void __init *plat_get_fdt(void)
|
||||
{
|
||||
if (fw_arg0 != -2)
|
||||
panic("Device-tree not present");
|
||||
return (void *)fw_arg1;
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
__dt_setup_arch(plat_get_fdt());
|
||||
}
|
||||
|
||||
#define DEFAULT_CPC_BASE_ADDR 0x1bde0000
|
||||
#define DEFAULT_CDMM_BASE_ADDR 0x1bdd0000
|
||||
|
||||
phys_addr_t mips_cpc_default_phys_base(void)
|
||||
{
|
||||
return DEFAULT_CPC_BASE_ADDR;
|
||||
}
|
||||
|
||||
phys_addr_t mips_cdmm_phys_base(void)
|
||||
{
|
||||
return DEFAULT_CDMM_BASE_ADDR;
|
||||
}
|
||||
|
||||
static void __init mips_nmi_setup(void)
|
||||
{
|
||||
void *base;
|
||||
|
||||
base = cpu_has_veic ?
|
||||
(void *)(CAC_BASE + 0xa80) :
|
||||
(void *)(CAC_BASE + 0x380);
|
||||
memcpy(base, except_vec_nmi, 0x80);
|
||||
flush_icache_range((unsigned long)base,
|
||||
(unsigned long)base + 0x80);
|
||||
}
|
||||
|
||||
static void __init mips_ejtag_setup(void)
|
||||
{
|
||||
void *base;
|
||||
extern char except_vec_ejtag_debug[];
|
||||
|
||||
base = cpu_has_veic ?
|
||||
(void *)(CAC_BASE + 0xa00) :
|
||||
(void *)(CAC_BASE + 0x300);
|
||||
memcpy(base, except_vec_ejtag_debug, 0x80);
|
||||
flush_icache_range((unsigned long)base,
|
||||
(unsigned long)base + 0x80);
|
||||
}
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
board_nmi_handler_setup = mips_nmi_setup;
|
||||
board_ejtag_handler_setup = mips_ejtag_setup;
|
||||
|
||||
mips_cm_probe();
|
||||
mips_cpc_probe();
|
||||
register_cps_smp_ops();
|
||||
|
||||
pr_info("SoC Type: %s\n", get_system_type());
|
||||
}
|
||||
|
||||
void __init device_tree_init(void)
|
||||
{
|
||||
if (!initial_boot_params)
|
||||
return;
|
||||
|
||||
unflatten_and_copy_device_tree();
|
||||
}
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Pistachio IRQ setup
|
||||
*
|
||||
* Copyright (C) 2014 Google, Inc.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <asm/cpu-features.h>
|
||||
#include <asm/irq_cpu.h>
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
pr_info("EIC is %s\n", cpu_has_veic ? "on" : "off");
|
||||
pr_info("VINT is %s\n", cpu_has_vint ? "on" : "off");
|
||||
|
||||
if (!cpu_has_veic)
|
||||
mips_cpu_irq_init();
|
||||
|
||||
irqchip_init();
|
||||
}
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Pistachio clocksource/timer setup
|
||||
*
|
||||
* Copyright (C) 2014 Google, Inc.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_clk.h>
|
||||
|
||||
#include <asm/mips-cps.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
unsigned int get_c0_compare_int(void)
|
||||
{
|
||||
return gic_get_c0_compare_int();
|
||||
}
|
||||
|
||||
int get_c0_perfcount_int(void)
|
||||
{
|
||||
return gic_get_c0_perfcount_int();
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
|
||||
|
||||
int get_c0_fdc_int(void)
|
||||
{
|
||||
return gic_get_c0_fdc_int();
|
||||
}
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct clk *clk;
|
||||
|
||||
of_clk_init(NULL);
|
||||
timer_probe();
|
||||
|
||||
np = of_get_cpu_node(0, NULL);
|
||||
if (!np) {
|
||||
pr_err("Failed to get CPU node\n");
|
||||
return;
|
||||
}
|
||||
|
||||
clk = of_clk_get(np, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
|
||||
return;
|
||||
}
|
||||
|
||||
mips_hpt_frequency = clk_get_rate(clk) / 2;
|
||||
clk_put(clk);
|
||||
}
|
||||
Loading…
Reference in New Issue