mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 10:49:33 +00:00
[SCSI] bfa: Brocade-1860 Fabric Adapter PLL init fixes.
- If flash controller is halted unconditionally, this results in illegal write access to flash controller register domain. Since flash controller registers are only accessible once s_clk is started - added logic to check for WGN status and halt flash controller only if it is already running. - Added check to wait for flash controller halt to be completed before proceeding with s_clk/l_clk initializations. - Removed unnecessary reset logic for PMM 1T memory and moved memory initialization after flash access enable. - Disable Brocade-1860 asic MBOX interrupt before PLL initialization. - Remove reset enable for S_CLK/L_CLK after both PLL initializations are complete. Signed-off-by: Krishna Gudipati <kgudipat@brocade.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
parent
a714134a85
commit
10a0737924
9 changed files with 176 additions and 139 deletions
|
@ -251,7 +251,39 @@ bfa_isr_reqq(struct bfa_s *bfa, int qid)
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void
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bfa_msix_all(struct bfa_s *bfa, int vec)
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{
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bfa_intx(bfa);
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u32 intr, qintr;
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int queue;
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intr = readl(bfa->iocfc.bfa_regs.intr_status);
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if (!intr)
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return;
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/*
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* RME completion queue interrupt
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*/
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qintr = intr & __HFN_INT_RME_MASK;
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if (qintr && bfa->queue_process) {
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for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++)
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bfa_isr_rspq(bfa, queue);
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}
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intr &= ~qintr;
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if (!intr)
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return;
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/*
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* CPE completion queue interrupt
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*/
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qintr = intr & __HFN_INT_CPE_MASK;
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if (qintr && bfa->queue_process) {
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for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++)
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bfa_isr_reqq(bfa, queue);
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}
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intr &= ~qintr;
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if (!intr)
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return;
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bfa_msix_lpu_err(bfa, intr);
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}
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bfa_boolean_t
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@ -469,6 +501,9 @@ bfa_iocfc_send_cfg(void *bfa_arg)
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/*
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* initialize IOC configuration info
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*/
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cfg_info->single_msix_vec = 0;
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if (bfa->msix.nvecs == 1)
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cfg_info->single_msix_vec = 1;
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cfg_info->endian_sig = BFI_IOC_ENDIAN_SIG;
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cfg_info->num_cqs = cfg->fwcfg.num_cqs;
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cfg_info->num_ioim_reqs = cpu_to_be16(cfg->fwcfg.num_ioim_reqs);
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@ -1080,12 +1115,6 @@ bfa_iocfc_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg,
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ioc->trcmod = bfa->trcmod;
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bfa_ioc_attach(&bfa->ioc, bfa, &bfa_iocfc_cbfn, &bfa->timer_mod);
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/*
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* Set FC mode for BFA_PCI_DEVICE_ID_CT_FC.
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*/
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if (pcidev->device_id == BFA_PCI_DEVICE_ID_CT_FC)
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bfa_ioc_set_fcmode(&bfa->ioc);
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bfa_ioc_pci_init(&bfa->ioc, pcidev, BFI_PCIFN_CLASS_FC);
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bfa_ioc_mbox_register(&bfa->ioc, bfa_mbox_isrs);
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@ -114,7 +114,7 @@ bfa_hwcb_msix_ctrl_install(struct bfa_s *bfa)
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return;
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if (bfa->msix.nvecs == 1) {
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for (i = BFI_MSIX_RME_QMAX_CB+1; i < BFI_MSIX_CB_MAX; i++)
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for (i = BFI_MSIX_CPE_QMIN_CB; i < BFI_MSIX_CB_MAX; i++)
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bfa->msix.handler[i] = bfa_msix_all;
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return;
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}
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@ -2399,12 +2399,6 @@ bfa_ioc_error_isr(struct bfa_ioc_s *ioc)
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bfa_fsm_send_event(ioc, IOC_E_HWERROR);
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}
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void
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bfa_ioc_set_fcmode(struct bfa_ioc_s *ioc)
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{
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ioc->fcmode = BFA_TRUE;
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}
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/*
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* return true if IOC is disabled
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*/
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@ -2592,35 +2586,7 @@ bfa_ioc_get_adapter_model(struct bfa_ioc_s *ioc, char *model)
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ioc_attr = ioc->attr;
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/*
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* model name
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*/
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if (ioc->asic_gen == BFI_ASIC_GEN_CT2) {
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int np = bfa_ioc_get_nports(ioc);
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char c;
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switch (ioc_attr->card_type) {
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case BFA_MFG_TYPE_PROWLER_F:
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case BFA_MFG_TYPE_PROWLER_N:
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case BFA_MFG_TYPE_PROWLER_C:
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snprintf(model, BFA_ADAPTER_MODEL_NAME_LEN,
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"%s-%u-%u",
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BFA_MFG_NAME, ioc_attr->card_type, np);
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break;
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case BFA_MFG_TYPE_PROWLER_D:
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if (ioc_attr->ic == BFA_MFG_IC_FC)
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c = 'F';
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else
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c = 'P';
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snprintf(model, BFA_ADAPTER_MODEL_NAME_LEN,
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"%s-%u-%u%c",
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BFA_MFG_NAME, ioc_attr->card_type, np, c);
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break;
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default:
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break;
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}
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} else
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snprintf(model, BFA_ADAPTER_MODEL_NAME_LEN, "%s-%u",
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snprintf(model, BFA_ADAPTER_MODEL_NAME_LEN, "%s-%u",
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BFA_MFG_NAME, ioc_attr->card_type);
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}
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@ -2711,12 +2677,6 @@ bfa_ioc_get_mfg_mac(struct bfa_ioc_s *ioc)
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return m;
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}
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bfa_boolean_t
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bfa_ioc_get_fcmode(struct bfa_ioc_s *ioc)
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{
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return ioc->fcmode || bfa_asic_id_cb(ioc->pcidev.device_id);
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}
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/*
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* Retrieve saved firmware trace from a prior IOC failure.
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*/
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@ -362,6 +362,7 @@ bfa_status_t bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode mode);
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} while (0)
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#define bfa_ioc_ownership_reset(__ioc) \
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((__ioc)->ioc_hwif->ioc_ownership_reset(__ioc))
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#define bfa_ioc_get_fcmode(__ioc) ((__ioc)->fcmode)
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#define bfa_ioc_lpu_read_stat(__ioc) do { \
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if ((__ioc)->ioc_hwif->ioc_lpu_read_stat) \
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((__ioc)->ioc_hwif->ioc_lpu_read_stat(__ioc)); \
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@ -414,8 +415,6 @@ bfa_status_t bfa_ioc_debug_fwtrc(struct bfa_ioc_s *ioc, void *trcdata,
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int *trclen);
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bfa_status_t bfa_ioc_debug_fwcore(struct bfa_ioc_s *ioc, void *buf,
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u32 *offset, int *buflen);
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void bfa_ioc_set_fcmode(struct bfa_ioc_s *ioc);
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bfa_boolean_t bfa_ioc_get_fcmode(struct bfa_ioc_s *ioc);
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bfa_boolean_t bfa_ioc_sem_get(void __iomem *sem_reg);
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void bfa_ioc_fwver_get(struct bfa_ioc_s *ioc,
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struct bfi_ioc_image_hdr_s *fwhdr);
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@ -564,10 +564,12 @@ bfa_ioc_set_ct2_hwif(struct bfa_ioc_s *ioc)
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* Temporary workaround for MSI-X resource allocation for catapult-2.
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*/
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#define HOSTFN_MSIX_DEFAULT 16
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#define HOSTFN_MSIX_VT_INDEX_MBOX_ERR 0x30138
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#define HOSTFN_MSIX_VT_OFST_NUMVT 0x3013c
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#define __MSIX_VT_NUMVT__MK 0x003ff800
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#define __MSIX_VT_NUMVT__SH 11
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#define __MSIX_VT_NUMVT_(_v) ((_v) << __MSIX_VT_NUMVT__SH)
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#define __MSIX_VT_OFST_ 0x000007ff
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void
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bfa_ioc_ct2_poweron(struct bfa_ioc_s *ioc)
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{
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@ -575,12 +577,17 @@ bfa_ioc_ct2_poweron(struct bfa_ioc_s *ioc)
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u32 r32;
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r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT);
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if (r32 & __MSIX_VT_NUMVT__MK)
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if (r32 & __MSIX_VT_NUMVT__MK) {
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writel(r32 & __MSIX_VT_OFST_,
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rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR);
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return;
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}
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writel(__MSIX_VT_NUMVT_(HOSTFN_MSIX_DEFAULT - 1) |
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HOSTFN_MSIX_DEFAULT * bfa_ioc_pcifn(ioc),
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rb + HOSTFN_MSIX_VT_OFST_NUMVT);
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writel(HOSTFN_MSIX_DEFAULT * bfa_ioc_pcifn(ioc),
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rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR);
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}
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bfa_status_t
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@ -649,17 +656,8 @@ bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode mode)
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return BFA_STATUS_OK;
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}
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static struct { u32 sclk, speed, half_speed; } ct2_pll[] = {
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{0}, /* unused */
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{__APP_PLL_SCLK_CLK_DIV2, 0, 0}, /* FC 8G */
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{0, 0, 0}, /* FC 16G */
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{__APP_PLL_SCLK_REFCLK_SEL | __APP_PLL_SCLK_CLK_DIV2, 0, /* ETH */
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__APP_LPUCLK_HALFSPEED},
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{0, 0, 0}, /* COMBO */
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};
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static void
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bfa_ioc_ct2_sclk_init(void __iomem *rb, enum bfi_asic_mode mode)
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bfa_ioc_ct2_sclk_init(void __iomem *rb)
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{
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u32 r32;
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writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
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/*
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* select clock speed based on mode
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* Ignore mode and program for the max clock (which is FC16)
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* Firmware/NFC will do the PLL init appropiately
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*/
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r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
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r32 &= ~(__APP_PLL_SCLK_REFCLK_SEL | __APP_PLL_SCLK_CLK_DIV2);
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writel(r32 | ct2_pll[mode].sclk, (rb + CT2_APP_PLL_SCLK_CTL_REG));
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writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
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/*
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* while doing PLL init dont clock gate ethernet subsystem
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@ -700,30 +699,10 @@ bfa_ioc_ct2_sclk_init(void __iomem *rb, enum bfi_asic_mode mode)
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* poll for s_clk lock or delay 1ms
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*/
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udelay(1000);
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/*
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* release soft reset on s_clk & l_clk
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*/
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r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
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writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,
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(rb + CT2_APP_PLL_SCLK_CTL_REG));
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/*
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* clock gating for ethernet subsystem if not in ethernet mode
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*/
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if (mode != BFI_ASIC_MODE_ETH) {
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r32 = readl((rb + CT2_CHIP_MISC_PRG));
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writel(r32 & ~__ETH_CLK_ENABLE_PORT0,
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(rb + CT2_CHIP_MISC_PRG));
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r32 = readl((rb + CT2_PCIE_MISC_REG));
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writel(r32 & ~__ETH_CLK_ENABLE_PORT1,
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(rb + CT2_PCIE_MISC_REG));
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}
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}
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static void
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bfa_ioc_ct2_lclk_init(void __iomem *rb, enum bfi_asic_mode mode)
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bfa_ioc_ct2_lclk_init(void __iomem *rb)
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{
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u32 r32;
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@ -737,35 +716,60 @@ bfa_ioc_ct2_lclk_init(void __iomem *rb, enum bfi_asic_mode mode)
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writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
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/*
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* set LPU speed
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* set LPU speed (set for FC16 which will work for other modes)
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*/
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r32 = readl((rb + CT2_CHIP_MISC_PRG));
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writel(r32 | ct2_pll[mode].speed,
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(rb + CT2_CHIP_MISC_PRG));
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writel(r32, (rb + CT2_CHIP_MISC_PRG));
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/*
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* set LPU half speed
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* set LPU half speed (set for FC16 which will work for other modes)
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*/
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r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
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writel(r32 | ct2_pll[mode].half_speed,
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(rb + CT2_APP_PLL_LCLK_CTL_REG));
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writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
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/*
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* set lclk for mode
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* set lclk for mode (set for FC16)
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*/
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r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
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r32 &= (__P_LCLK_PLL_LOCK | __APP_LPUCLK_HALFSPEED);
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if (mode == BFI_ASIC_MODE_FC || mode == BFI_ASIC_MODE_FC16 ||
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mode == BFI_ASIC_MODE_ETH)
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r32 |= 0x20c1731b;
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else
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r32 |= 0x2081731b;
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r32 |= 0x20c1731b;
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writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
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/*
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* poll for s_clk lock or delay 1ms
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*/
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udelay(1000);
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}
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static void
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bfa_ioc_ct2_mem_init(void __iomem *rb)
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{
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u32 r32;
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r32 = readl((rb + PSS_CTL_REG));
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r32 &= ~__PSS_LMEM_RESET;
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writel(r32, (rb + PSS_CTL_REG));
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udelay(1000);
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writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG));
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udelay(1000);
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writel(0, (rb + CT2_MBIST_CTL_REG));
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}
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void
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bfa_ioc_ct2_mac_reset(void __iomem *rb)
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{
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u32 r32;
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bfa_ioc_ct2_sclk_init(rb);
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bfa_ioc_ct2_lclk_init(rb);
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/*
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* release soft reset on s_clk & l_clk
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*/
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r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
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writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,
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(rb + CT2_APP_PLL_SCLK_CTL_REG));
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/*
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* release soft reset on s_clk & l_clk
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@ -773,61 +777,83 @@ bfa_ioc_ct2_lclk_init(void __iomem *rb, enum bfi_asic_mode mode)
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r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
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writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,
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(rb + CT2_APP_PLL_LCLK_CTL_REG));
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/* put port0, port1 MAC & AHB in reset */
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writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET),
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rb + CT2_CSI_MAC_CONTROL_REG(0));
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writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET),
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rb + CT2_CSI_MAC_CONTROL_REG(1));
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}
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static void
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bfa_ioc_ct2_mem_init(void __iomem *rb, enum bfi_asic_mode mode)
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{
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bfa_boolean_t fcmode;
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u32 r32;
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fcmode = (mode == BFI_ASIC_MODE_FC) || (mode == BFI_ASIC_MODE_FC16);
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if (!fcmode) {
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writel(__PMM_1T_PNDB_P | __PMM_1T_RESET_P,
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(rb + CT2_PMM_1T_CONTROL_REG_P0));
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writel(__PMM_1T_PNDB_P | __PMM_1T_RESET_P,
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(rb + CT2_PMM_1T_CONTROL_REG_P1));
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}
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r32 = readl((rb + PSS_CTL_REG));
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r32 &= ~__PSS_LMEM_RESET;
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writel(r32, (rb + PSS_CTL_REG));
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udelay(1000);
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if (!fcmode) {
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writel(__PMM_1T_PNDB_P, (rb + CT2_PMM_1T_CONTROL_REG_P0));
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writel(__PMM_1T_PNDB_P, (rb + CT2_PMM_1T_CONTROL_REG_P1));
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}
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writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG));
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udelay(1000);
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writel(0, (rb + CT2_MBIST_CTL_REG));
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}
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#define CT2_NFC_MAX_DELAY 1000
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bfa_status_t
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bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode mode)
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{
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u32 r32;
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u32 wgn, r32;
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int i;
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/*
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* Initialize PLL if not already done by NFC
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*/
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r32 = readl((rb + CT2_WGN_STATUS));
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wgn = readl(rb + CT2_WGN_STATUS);
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if (!(wgn & __GLBL_PF_VF_CFG_RDY)) {
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writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_SET_REG);
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for (i = 0; i < CT2_NFC_MAX_DELAY; i++) {
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r32 = readl(rb + CT2_NFC_CSR_SET_REG);
|
||||
if (r32 & __NFC_CONTROLLER_HALTED)
|
||||
break;
|
||||
udelay(1000);
|
||||
}
|
||||
}
|
||||
|
||||
writel(__HALT_NFC_CONTROLLER, (rb + CT2_NFC_CSR_SET_REG));
|
||||
/*
|
||||
* Mask the interrupts and clear any
|
||||
* pending interrupts.
|
||||
*/
|
||||
writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK));
|
||||
writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK));
|
||||
|
||||
bfa_ioc_ct2_sclk_init(rb, mode);
|
||||
bfa_ioc_ct2_lclk_init(rb, mode);
|
||||
bfa_ioc_ct2_mem_init(rb, mode);
|
||||
r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));
|
||||
if (r32 == 1) {
|
||||
writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT));
|
||||
readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));
|
||||
}
|
||||
r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));
|
||||
if (r32 == 1) {
|
||||
writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT));
|
||||
readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));
|
||||
}
|
||||
|
||||
bfa_ioc_ct2_mac_reset(rb);
|
||||
bfa_ioc_ct2_sclk_init(rb);
|
||||
bfa_ioc_ct2_lclk_init(rb);
|
||||
|
||||
/*
|
||||
* release soft reset on s_clk & l_clk
|
||||
*/
|
||||
r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
|
||||
writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET,
|
||||
(rb + CT2_APP_PLL_SCLK_CTL_REG));
|
||||
|
||||
/*
|
||||
* release soft reset on s_clk & l_clk
|
||||
*/
|
||||
r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
|
||||
writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET,
|
||||
(rb + CT2_APP_PLL_LCLK_CTL_REG));
|
||||
|
||||
/*
|
||||
* Announce flash device presence, if flash was corrupted.
|
||||
*/
|
||||
if (r32 == (__WGN_READY | __GLBL_PF_VF_CFG_RDY)) {
|
||||
writel(0, (rb + PSS_GPIO_OUT_REG));
|
||||
writel(1, (rb + PSS_GPIO_OE_REG));
|
||||
if (wgn == (__WGN_READY | __GLBL_PF_VF_CFG_RDY)) {
|
||||
r32 = readl((rb + PSS_GPIO_OUT_REG));
|
||||
writel(r32 & ~1, (rb + PSS_GPIO_OUT_REG));
|
||||
r32 = readl((rb + PSS_GPIO_OE_REG));
|
||||
writel(r32 | 1, (rb + PSS_GPIO_OE_REG));
|
||||
}
|
||||
|
||||
bfa_ioc_ct2_mem_init(rb);
|
||||
|
||||
writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG));
|
||||
writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG));
|
||||
return BFA_STATUS_OK;
|
||||
|
|
|
@ -784,11 +784,14 @@ bfad_pci_init(struct pci_dev *pdev, struct bfad_s *bfad)
|
|||
pci_set_master(pdev);
|
||||
|
||||
|
||||
if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)
|
||||
if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
|
||||
if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
|
||||
(pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
|
||||
if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
|
||||
(pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
|
||||
printk(KERN_ERR "pci_set_dma_mask fail %p\n", pdev);
|
||||
goto out_release_region;
|
||||
}
|
||||
}
|
||||
|
||||
bfad->pci_bar0_kva = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
|
||||
bfad->pci_bar2_kva = pci_iomap(pdev, 2, pci_resource_len(pdev, 2));
|
||||
|
@ -1291,6 +1294,7 @@ bfad_setup_intr(struct bfad_s *bfad)
|
|||
u32 mask = 0, i, num_bit = 0, max_bit = 0;
|
||||
struct msix_entry msix_entries[MAX_MSIX_ENTRY];
|
||||
struct pci_dev *pdev = bfad->pcidev;
|
||||
u16 reg;
|
||||
|
||||
/* Call BFA to get the msix map for this PCI function. */
|
||||
bfa_msix_getvecs(&bfad->bfa, &mask, &num_bit, &max_bit);
|
||||
|
@ -1320,6 +1324,13 @@ bfad_setup_intr(struct bfad_s *bfad)
|
|||
goto line_based;
|
||||
}
|
||||
|
||||
/* Disable INTX in MSI-X mode */
|
||||
pci_read_config_word(pdev, PCI_COMMAND, ®);
|
||||
|
||||
if (!(reg & PCI_COMMAND_INTX_DISABLE))
|
||||
pci_write_config_word(pdev, PCI_COMMAND,
|
||||
reg | PCI_COMMAND_INTX_DISABLE);
|
||||
|
||||
/* Save the vectors */
|
||||
for (i = 0; i < bfad->nvec; i++) {
|
||||
bfa_trc(bfad, msix_entries[i].vector);
|
||||
|
|
|
@ -253,7 +253,7 @@ struct bfi_ioc_attr_s {
|
|||
u32 adapter_prop; /* adapter properties */
|
||||
u16 maxfrsize; /* max receive frame size */
|
||||
char asic_rev;
|
||||
u8 ic; /* initial capability */
|
||||
u8 rsvd_d;
|
||||
char fw_version[BFA_VERSION_LEN];
|
||||
char optrom_version[BFA_VERSION_LEN];
|
||||
struct bfa_mfg_vpd_s vpd;
|
||||
|
|
|
@ -48,7 +48,8 @@ struct bfi_iocfc_cfg_s {
|
|||
u32 endian_sig; /* endian signature of host */
|
||||
__be16 num_ioim_reqs;
|
||||
__be16 num_fwtio_reqs;
|
||||
u8 rsvd[4];
|
||||
u8 single_msix_vec;
|
||||
u8 rsvd[3];
|
||||
|
||||
/*
|
||||
* Request and response circular queue base addresses, size and
|
||||
|
|
|
@ -277,6 +277,8 @@ enum {
|
|||
#define CT2_LPU1_HOSTFN_CMD_STAT (CT2_PCI_CPQ_BASE + 0x8c)
|
||||
#define CT2_HOSTFN_LPU0_READ_STAT (CT2_PCI_CPQ_BASE + 0x90)
|
||||
#define CT2_HOSTFN_LPU1_READ_STAT (CT2_PCI_CPQ_BASE + 0x94)
|
||||
#define CT2_LPU0_HOSTFN_MBOX0_MSK (CT2_PCI_CPQ_BASE + 0x98)
|
||||
#define CT2_LPU1_HOSTFN_MBOX0_MSK (CT2_PCI_CPQ_BASE + 0x9C)
|
||||
#define CT2_HOST_SEM0_REG 0x000148f0
|
||||
#define CT2_HOST_SEM1_REG 0x000148f4
|
||||
#define CT2_HOST_SEM2_REG 0x000148f8
|
||||
|
@ -337,6 +339,15 @@ enum {
|
|||
#define __GLBL_PF_VF_CFG_RDY 0x00000200
|
||||
#define CT2_NFC_CSR_SET_REG 0x00027424
|
||||
#define __HALT_NFC_CONTROLLER 0x00000002
|
||||
#define __NFC_CONTROLLER_HALTED 0x00001000
|
||||
|
||||
#define CT2_CSI_MAC0_CONTROL_REG 0x000270d0
|
||||
#define __CSI_MAC_RESET 0x00000010
|
||||
#define __CSI_MAC_AHB_RESET 0x00000008
|
||||
#define CT2_CSI_MAC1_CONTROL_REG 0x000270d4
|
||||
#define CT2_CSI_MAC_CONTROL_REG(__n) \
|
||||
(CT2_CSI_MAC0_CONTROL_REG + \
|
||||
(__n) * (CT2_CSI_MAC1_CONTROL_REG - CT2_CSI_MAC0_CONTROL_REG))
|
||||
|
||||
/*
|
||||
* Name semaphore registers based on usage
|
||||
|
|
Loading…
Reference in a new issue