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[ARM] nommu: MPU support in boot/compressed/head.S
This patch adds MPU support in boot/compressed/head.S. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -2,6 +2,7 @@
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* linux/arch/arm/boot/compressed/head.S
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*
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* Copyright (C) 1996-2002 Russell King
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* Copyright (C) 2004 Hyok S. Choi (MPU support)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -320,6 +321,62 @@ params: ldr r0, =params_phys
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cache_on: mov r3, #8 @ cache_on function
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b call_cache_fn
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/*
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* Initialize the highest priority protection region, PR7
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* to cover all 32bit address and cacheable and bufferable.
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*/
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__armv4_mpu_cache_on:
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mov r0, #0x3f @ 4G, the whole
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mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
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mcr p15, 0, r0, c6, c7, 1
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mov r0, #0x80 @ PR7
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mcr p15, 0, r0, c2, c0, 0 @ D-cache on
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mcr p15, 0, r0, c2, c0, 1 @ I-cache on
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mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
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mov r0, #0xc000
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mcr p15, 0, r0, c5, c0, 1 @ I-access permission
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mcr p15, 0, r0, c5, c0, 0 @ D-access permission
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
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mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
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mrc p15, 0, r0, c1, c0, 0 @ read control reg
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@ ...I .... ..D. WC.M
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orr r0, r0, #0x002d @ .... .... ..1. 11.1
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orr r0, r0, #0x1000 @ ...1 .... .... ....
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mcr p15, 0, r0, c1, c0, 0 @ write control reg
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
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mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
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mov pc, lr
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__armv3_mpu_cache_on:
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mov r0, #0x3f @ 4G, the whole
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mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
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mov r0, #0x80 @ PR7
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mcr p15, 0, r0, c2, c0, 0 @ cache on
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mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
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mov r0, #0xc000
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mcr p15, 0, r0, c5, c0, 0 @ access permission
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mov r0, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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mrc p15, 0, r0, c1, c0, 0 @ read control reg
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@ .... .... .... WC.M
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orr r0, r0, #0x000d @ .... .... .... 11.1
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mov r0, #0
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mcr p15, 0, r0, c1, c0, 0 @ write control reg
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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mov pc, lr
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__setup_mmu: sub r3, r4, #16384 @ Page directory size
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bic r3, r3, #0xff @ Align the pointer
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bic r3, r3, #0x3f00
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@ -496,6 +553,18 @@ proc_types:
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b __armv4_mmu_cache_off
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mov pc, lr
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.word 0x41007400 @ ARM74x
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.word 0xff00ff00
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b __armv3_mpu_cache_on
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b __armv3_mpu_cache_off
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b __armv3_mpu_cache_flush
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.word 0x41009400 @ ARM94x
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.word 0xff00ff00
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b __armv4_mpu_cache_on
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b __armv4_mpu_cache_off
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b __armv4_mpu_cache_flush
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.word 0x00007000 @ ARM7 IDs
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.word 0x0000f000
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mov pc, lr
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@ -562,6 +631,24 @@ proc_types:
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cache_off: mov r3, #12 @ cache_off function
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b call_cache_fn
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__armv4_mpu_cache_off:
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mrc p15, 0, r0, c1, c0
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bic r0, r0, #0x000d
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mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
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mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
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mov pc, lr
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__armv3_mpu_cache_off:
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mrc p15, 0, r0, c1, c0
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bic r0, r0, #0x000d
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mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
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mov r0, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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mov pc, lr
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__armv4_mmu_cache_off:
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mrc p15, 0, r0, c1, c0
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bic r0, r0, #0x000d
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@ -601,6 +688,24 @@ cache_clean_flush:
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mov r3, #16
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b call_cache_fn
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__armv4_mpu_cache_flush:
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mov r2, #1
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mov r3, #0
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mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
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mov r1, #7 << 5 @ 8 segments
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1: orr r3, r1, #63 << 26 @ 64 entries
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2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 5
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bcs 1b @ segments 7 to 0
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teq r2, #0
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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__armv6_mmu_cache_flush:
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mov r1, #0
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mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
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@ -638,6 +743,7 @@ no_cache_id:
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mov pc, lr
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__armv3_mmu_cache_flush:
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__armv3_mpu_cache_flush:
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mov r1, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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mov pc, lr
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