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drm/amd/powerplay: use ffs/fls instead of implementing our own
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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31a47dcab8
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10cd19c877
1 changed files with 4 additions and 23 deletions
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@ -4489,7 +4489,6 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
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enum pp_clock_type type, uint32_t mask)
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{
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struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
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int i;
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if (hwmgr->request_dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
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AMD_DPM_FORCED_LEVEL_LOW |
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@ -4498,17 +4497,8 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
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switch (type) {
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case PP_SCLK:
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for (i = 0; i < 32; i++) {
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if (mask & (1 << i))
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break;
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}
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data->smc_state_table.gfx_boot_level = i;
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for (i = 31; i >= 0; i--) {
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if (mask & (1 << i))
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break;
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}
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data->smc_state_table.gfx_max_level = i;
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data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
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data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
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PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
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"Failed to upload boot level to lowest!",
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@ -4520,17 +4510,8 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
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break;
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case PP_MCLK:
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for (i = 0; i < 32; i++) {
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if (mask & (1 << i))
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break;
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}
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data->smc_state_table.mem_boot_level = i;
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for (i = 31; i >= 0; i--) {
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if (mask & (1 << i))
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break;
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}
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data->smc_state_table.mem_max_level = i;
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data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;
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data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;
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PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
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"Failed to upload boot level to lowest!",
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