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clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset
Parameterise the offset of control bits within the FRQCRC register for Z and Z2 clocks. This is in preparation for supporting the Z2 clock on the R-Car E3 (r8a77990) SoC which uses a different offset for control bits to other, already, supported SoCs. As suggested by Geert Uytterhoeven. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
parent
20cc05ba04
commit
10d9ea5100
6 changed files with 13 additions and 20 deletions
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@ -71,8 +71,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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/* Core Clock Outputs */
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DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2),
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DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2),
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DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
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DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0),
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DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
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@ -74,8 +74,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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/* Core Clock Outputs */
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DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2),
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DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2),
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DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
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DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0),
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DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
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@ -74,8 +74,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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/* Core Clock Outputs */
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DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2),
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DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2),
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DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
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DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0),
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DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
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@ -71,7 +71,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
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DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
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/* Core Clock Outputs */
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DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2),
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DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
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DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
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@ -88,8 +88,6 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
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#define CPG_FRQCRB 0x00000004
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#define CPG_FRQCRB_KICK BIT(31)
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#define CPG_FRQCRC 0x000000e0
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#define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8)
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#define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0)
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struct cpg_z_clk {
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struct clk_hw hw;
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@ -180,8 +178,8 @@ static const struct clk_ops cpg_z_clk_ops = {
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static struct clk * __init cpg_z_clk_register(const char *name,
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const char *parent_name,
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void __iomem *reg,
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unsigned long mask,
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unsigned int div)
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unsigned int div,
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unsigned int offset)
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{
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struct clk_init_data init;
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struct cpg_z_clk *zclk;
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@ -200,7 +198,7 @@ static struct clk * __init cpg_z_clk_register(const char *name,
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zclk->reg = reg + CPG_FRQCRC;
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zclk->kick_reg = reg + CPG_FRQCRB;
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zclk->hw.init = &init;
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zclk->mask = mask;
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zclk->mask = GENMASK(offset + 4, offset);
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zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
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clk = clk_register(NULL, &zclk->hw);
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@ -661,14 +659,9 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
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break;
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case CLK_TYPE_GEN3_Z:
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return cpg_z_clk_register(core->name, __clk_get_name(parent),
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base, CPG_FRQCRC_ZFC_MASK,
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core->div);
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case CLK_TYPE_GEN3_Z2:
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return cpg_z_clk_register(core->name, __clk_get_name(parent),
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base, CPG_FRQCRC_Z2FC_MASK,
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core->div);
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base, core->div, core->offset);
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case CLK_TYPE_GEN3_OSC:
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/*
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@ -52,8 +52,8 @@ enum rcar_gen3_clk_types {
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
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(_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
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#define DEF_GEN3_Z(_name, _id, _type, _parent, _div) \
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DEF_BASE(_name, _id, _type, _parent, .div = _div)
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#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
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DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
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struct rcar_gen3_cpg_pll_config {
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u8 extal_div;
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